EP3C10E144C8N Altera, EP3C10E144C8N Datasheet - Page 114
![IC CYCLONE III FPGA 10K 144-EQFP](/photos/6/73/67314/ep3c10e144c8n_sml.jpg)
EP3C10E144C8N
Manufacturer Part Number
EP3C10E144C8N
Description
IC CYCLONE III FPGA 10K 144-EQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10E144C8N.pdf
(274 pages)
Specifications of EP3C10E144C8N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
94
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2427
EP3C10E144C8N
EP3C10E144C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C10E144C8N
Manufacturer:
ALTERA47
Quantity:
516
Part Number:
EP3C10E144C8N
Manufacturer:
ALTERA
Quantity:
20 000
6–14
Figure 6–6. Cyclone III Device Family HSTL I/O Standard Termination
Figure 6–7. Cyclone III Device Family SSTL I/O Standard Termination
Differential I/O Standard Termination
Cyclone III Device Handbook, Volume 1
Termination
Termination
and without
Calibration
On-Board
OCT with
External
Termination
and without
Termination
Calibration
OCT with
On-Board
External
Cyclone III Device
Family Series OCT
Transmitter
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the bus
The Cyclone III device family supports differential SSTL-2 and SSTL-18, differential
HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and differential
LVPECL.
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
50
50
25
SSTL Class I
HSTL Class I
50
50
50
V REF
50
V REF
50
V REF
50
50
V REF
50
V TT
V TT
V TT
V TT
(Figure 6–8
Receiver
Receiver
Receiver
Receiver
and
Cyclone III Device
Family Series OCT
Figure
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
Transmitter
25
25
Chapter 6: I/O Features in the Cyclone III Device Family
6–9).
V TT
V TT
25
50
HSTL Class II
50
SSTL Class II
50
50
V TT
V TT
50
50
V REF
© December 2009 Altera Corporation
50
50
V REF
Termination Scheme for I/O Standards
50
50
V TT
50
V REF
V REF
V TT
50
V TT
V TT
Receiver
Receiver
Receiver
Receiver