EP1S25F780C7N Altera, EP1S25F780C7N Datasheet - Page 31

IC STRATIX FPGA 25K LE 780-FBGA

EP1S25F780C7N

Manufacturer Part Number
EP1S25F780C7N
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F780C7N

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1860
EP1S25F780C7N

Available stocks

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Manufacturer
Quantity
Price
Part Number:
EP1S25F780C7N
Manufacturer:
ALTERA
Quantity:
648
Part Number:
EP1S25F780C7N
Manufacturer:
Altera
Quantity:
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Part Number:
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Manufacturer:
ALTERA
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Part Number:
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Manufacturer:
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Quantity:
20 000
Altera Corporation
July 2005
Figure 2–10. LUT Chain & Register Chain Interconnects
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down.
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks, including DSP blocks, TriMatrix
memory blocks, and vertical IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect.
C4 interconnects can drive each other to extend their range as well as
drive row interconnects for column-to-column connections.
Interconnect
Adjacent LE
Routing to
LUT Chain
Local
Figure 2–11
Local Interconnect
Routing Among LEs
in the LAB
shows the C4 interconnect connections
LE 10
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
Stratix Device Handbook, Volume 1
Register Chain
Routing to Adjacent
LE's Register Input
Stratix Architecture
2–17

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