EP1S25F780C5 Altera, EP1S25F780C5 Datasheet - Page 238
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EP1S25F780C5
Manufacturer Part Number
EP1S25F780C5
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C5
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1120
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C5
Manufacturer:
AT
Quantity:
186
Company:
Part Number:
EP1S25F780C5
Manufacturer:
ALTERA
Quantity:
315
Company:
Part Number:
EP1S25F780C5
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP1S25F780C5AA
Manufacturer:
ALTERA
Quantity:
269
Company:
Part Number:
EP1S25F780C5N
Manufacturer:
ALTERA
Quantity:
3 000
Timing Model
4–68
Stratix Device Handbook, Volume 1
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
Parameter
12 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
12 mA
2 mA
4 mA
8 mA
4 mA
8 mA
2 mA
8 mA
2 mA
8 mA
2 mA
4 mA
8 mA
-5 Speed Grade
Tables 4–105
with column and row I/O pins for both fast and slow slew rates. If an I/O
standard is selected other than 3.3-V LVTTL 4mA or LVCMOS 2 mA with
a fast slew rate, add the selected delay to the external t
t
page 4–36
Min
XZ
, t
ZX
, t
1,895
1,895
1,347
2,517
1,304
6,680
3,275
1,589
1,895
–157
Max
956
189
636
561
834
504
194
960
960
XZPLL
16
50
50
50
50
0
0
9
through
through
, and t
-6 Speed Grade
Min
Table 4–96 on page
ZXPLL
4–108
1,990
1,004
1,990
1,414
2,643
1,369
1,008
1,008
7,014
3,439
1,668
1,990
–165
Max
I/O parameters shown in
198
668
589
875
529
203
17
52
52
52
52
0
0
9
show the output adder delays associated
-7 Speed Grade
Min
4–56.
1,990
1,004
1,990
1,414
2,643
1,369
1,008
1,008
7,014
3,439
1,668
1,990
–165
Max
198
668
589
875
529
203
17
52
52
52
52
0
0
9
-8 Speed Grade
Min
Table 4–55 on
OUTCO
Altera Corporation
1,990
1,004
1,990
1,414
2,643
1,369
1,008
1,008
7,014
3,439
1,668
1,990
–165
January 2006
Max
198
668
589
875
529
203
, t
52
17
52
52
52
0
0
9
OUTCOPLL
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
,