EP1S25F780C5 Altera, EP1S25F780C5 Datasheet - Page 7
![IC STRATIX FPGA 25K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S25F780C5
Manufacturer Part Number
EP1S25F780C5
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C5
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1120
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C5
Manufacturer:
AT
Quantity:
186
Company:
Part Number:
EP1S25F780C5
Manufacturer:
ALTERA
Quantity:
315
Company:
Part Number:
EP1S25F780C5
Manufacturer:
ALTERA
Quantity:
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Company:
Part Number:
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Manufacturer:
ALTERA
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Company:
Part Number:
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Manufacturer:
ALTERA
Quantity:
3 000
Altera Corporation
Chapter
4
5
September 2004, v2.1
October 2003, v2.1
April 2003, v1.0
July 2003, v2.0
Date/Version
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Added -8 speed grade information.
Updated performance information in
Updated timing information in
Updated delay information in
Updated programmable delay information in
4–103.
Updated clock rates in
Updated speed grade information in the introduction on page 4-1.
Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD
are specified.
Added note 6 to Table 4-32.
Updated Stratix Performance Table 4-35.
Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 4-
93. The Stratix timing models are final for all devices.
Updated Stratix IOE programmable delay chains in Tables 4-100 to 4-
101.
Added single-ended I/O standard output pin delay adders for loading
in Table 4-102.
Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107.
Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-
115.
Updated EPLL specification and fast PLL specification in Tables 4-
116 to 4-120.
Updated reference to device pin-outs on
device pin-outs are no longer included in this manual and are now
available on the Altera web site.
No new changes in Stratix Device Handbook v2.0.
Tables 4–114
Changes Made
Tables 4–103
Tables 4–55
Stratix Device Family Data Sheet
Table
through 4–123.
page 5–1
4–36.
through 4–96.
through 4–108.
Tables 4–100
to indicate that
Section I–7
and