EP3C10U256C6N Altera, EP3C10U256C6N Datasheet - Page 228
![IC CYCLONE III FPGA 10K 256-UBGA](/photos/6/73/67381/ep3c10u256c6n_sml.jpg)
EP3C10U256C6N
Manufacturer Part Number
EP3C10U256C6N
Description
IC CYCLONE III FPGA 10K 256-UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10U256C6N.pdf
(274 pages)
Specifications of EP3C10U256C6N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
500MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2433
EP3C10U256C6N
EP3C10U256C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9–68
Table 9–21. Cyclone III Device Family Configuration Pin Summary (Part 2 of 2)
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 1 of 4)
Cyclone III Device Handbook, Volume 1
Notes to
(1) In Cyclone III devices, the CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain
(2) AP configuration is for Cyclone III devices only.
MSEL [3..0]
nCONFIG
nSTATUS
Bank
5
5
Pin Name
output in the CRC Error Detection tab from the Device and Pin Options dialog box.
Table
DEV_OE
DEV_CLRn
9–21:
Description
Mode
User
N/A
N/A
N/A
Table 9–22
your board for successful configuration. Some of these pins may not be required for
your configuration scheme.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration
Scheme
lists the dedicated configuration pins that must be connected properly on
All
All
All
Input/Output
Input
Input
Bidirectional
open-drain
Pin Type
Input
Input
Dedicated
—
—
4-bit configuration input that sets the Cyclone III device
family configuration scheme. These pins must be hardwired
to V
pull-down resistors that are always active.
Some of the smaller devices or package options of
Cyclone III devices do not have the MSEL[3] pin; therefore,
the AP configuration scheme is not supported.
Configuration control input. Pulling this pin low with external
circuitry during user mode causes the Cyclone III device
family to lose its configuration data, enter a reset state, and
tri-state all I/O pins. Returning this pin to a logic-high level
starts a reconfiguration.
The Cyclone III device family drives nSTATUS low
immediately after power-up and releases it after the POR
time.
■
■
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If you use a
configuration device, driving nSTATUS low causes the
configuration device to attempt to configure the device, but
because the device ignores transitions on nSTATUS in user
mode, the device does not reconfigure. To start a
reconfiguration, nCONFIG must be pulled low.
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source (for example, another
Cyclone III device family) drives the nSTATUS pin low
during configuration or initialization, the target device
enters an error state.
C CA
or GND. The MSEL[3..0] pins have internal 9-kΩ
Powered By
V
V
CC IO
CC IO
Description
© December 2009 Altera Corporation
Configuration Mode
Optional, AP
Optional, AP
Configuration Features
(2)
(2)
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