EP3C10U256C6N Altera, EP3C10U256C6N Datasheet - Page 90
![IC CYCLONE III FPGA 10K 256-UBGA](/photos/6/73/67381/ep3c10u256c6n_sml.jpg)
EP3C10U256C6N
Manufacturer Part Number
EP3C10U256C6N
Description
IC CYCLONE III FPGA 10K 256-UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10U256C6N.pdf
(274 pages)
Specifications of EP3C10U256C6N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
500MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2433
EP3C10U256C6N
EP3C10U256C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–26
Figure 5–21. PLL Reconfiguration Scan Chain
Cyclone III Device Handbook, Volume 1
configupdate
scandataout
scanclkena
scandone
scandata
scanclk
areset
1
1
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, not all counters update simultaneously.
To reconfigure the PLL counters, perform the following steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 144 bits have been scanned into the scan chain, the scanclkena signal is
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high indicating that the PLL is being reconfigured. A
6. Reset the PLL using the areset signal if you make any changes to the M, N,
7. You can repeat steps
Figure 5–21
When reconfiguring the counter clock frequency, the corresponding counter phase
shift settings cannot be reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the same non-zero phase
shift setting (for example, 90°) on the clock output, you must reconfigure the phase
shift after reconfiguring the counter clock frequency.
Dn_old
the first bit of scandata (Dn).
scanclk.
deasserted to prevent inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
falling edge indicates that the PLL counters have been updated with new settings.
post-scale output C counters, or the I
Dn
shows a functional simulation of the PLL reconfiguration feature.
1
through
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5
to reconfigure the PLL any number of times.
CP
, R, C settings.
D0_old
LSB
D0
© December 2009 Altera Corporation
Dn
PLL Reconfiguration
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