EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 22
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
Quantity:
2 350
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
Quantity:
160
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA53
Quantity:
612
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP3C25F324C8NES
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–22
Cyclone III Device Handbook, Volume 2
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications
of 2)
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) t
f
frequency)
HSIODR
SW
Input jitter
tolerance
t
Notes to
(1) LVDS receiver is supported at all banks.
(2) t
LOCK
HSC LK
LOCK
(2)
(2)
Symbol
Symbol
LOC K
(input clock
LOC K
Table
Table
is the time required for the PLL to lock from the end of device configuration.
is the time required for the PLL to lock from the end of device configuration.
1–30:
1–31:
Modes
Modes
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
—
—
Min
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
—
—
—
C6
C6
437.5
437.5
437.5
437.5
437.5
437.5
437.5
Max
Max
875
875
875
875
875
400
500
200
500
1
1
Min
100
Min
10
10
10
10
10
10
80
70
40
20
10
—
—
—
—
—
—
C7, I7
C7, I7
Chapter 1: Cyclone III Device Data Sheet
402.5
402.5
Max
Max
370
370
370
370
370
740
740
740
740
740
400
500
200
500
1
1
© January 2010 Altera Corporation
(Note 1)
Min
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
—
—
—
C8, A7
C8, A7
Switching Characteristics
(Note 1)
402.5
402.5
Max
Max
320
320
320
320
320
640
640
640
640
640
400
550
200
550
1
1
(Part 2
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ms
ms
ps
ps
ps
ps