EP1K50QI208-2 Altera, EP1K50QI208-2 Datasheet - Page 37
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EP1K50QI208-2
Manufacturer Part Number
EP1K50QI208-2
Description
IC ACEX 1K FPGA 50K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K50QI208-2
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
147
Number Of Gates
199000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
ACEX™ 1K
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# I/os (max)
147
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1010
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K50QI208-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1K50QI208-2N
Manufacturer:
ALTERA21
Quantity:
53
Altera Corporation
Figure 19. Specifications for the Incoming & Generated Clocks
Note:
(1)
The t
period.
I
ClockLock
Generated
Clock
parameter refers to the nominal input clock period; the t
Input
Clock
t
R
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the Altera
software, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration.
specifications.
t
OUTDUTY
t
CLK1
t
F
t
INDUTY
t
t
O
O
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 19
t
I +
t
O +
t
INCLKSTB
t
JITTER
shows the incoming and generated clock
O
parameter refers to the nominal output clock
t
Note (1)
O
t
JITTER
t
I +
t
CLKDEV
37
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