EP3C40F484I7N Altera, EP3C40F484I7N Datasheet - Page 17

• Manufacturer Part Number: EP3C40F484I7N
• Description: IC CYCLONE III FPGA 40K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484I7N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2548

Board Design Considerations
Board Design Considerations
I/O Consideration
© November 2008 Altera Corporation
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This section contains the information for your consideration when designing the
board.
3.3/3.0/2.5V LVTTL/LVCMOS Interface
Cyclone III devices are designed to support interface voltage levels from 1.2 V up to
3.3 V to accommodate the need for flexible I/O interface implementation. You can use
Cyclone III devices to directly drive out 3.3-V LVTTL at up to 8 mA and 3.3-V
LVCMOS at up to 2 mA. When using Cyclone III devices as a receiver in 3.3/3.0/2.5-V
LVTTL/LVCMOS systems, you must follow the operating conditions including the
Cyclone III absolute maximum DC input voltage and maximum allowed
overshoot/undershoot voltage conditions.
For the values of the absolute maximum DC input voltage and maximum allowed
overshoot/undershoot voltage, refer to the
Switching Characteristics
Follow the guidelines in
LVTTL/LVCMOS I/O Systems
Cyclone III with 3.3/3.0/2.5 V voltage levels.
Pad Placement Consideration
The V
bank. To maintain an acceptable noise level on the V
on placement of single-ended I/O pads in relation to differential pads. The Quartus II
software automatically checks for these restrictions.
When single-ended voltage-referenced inputs are used in a bank, the Quartus II
software automatically checks for restrictions about the placement of outputs in
relation to V
maintain acceptable noise level on the V
noise from shifting the V
The Pad Placement and DC Guidelines section in the
chapter in volume 1 of the Cyclone III Device Handbook provides placement guidelines
for single-ended pads with respect to differential pads for each supported differential
I/O standards. Placement guidelines for input, output and bidirectional pads when
voltage referenced input pads exist in a bank are also available in the same section.
In specific applications, you can relax the restriction checks in the Quartus II software.
For instance, if you have a non-toggling single-ended pin, you can place it closer to a
differential pin safely, thereby bypassing pin placement checks. To set this in the
Quartus II software, assign 0 MHz toggle rate to Toggle Rate assignments for the pin
in the Assignment Editor. The Output Enable Group assignment is another setting
that is useful especially in external memory interfaces to allow efficient placement of
output or bidirectional pins in a V
the group.
CCIO
supply for a bank is susceptible to noise from switching outputs in the
REF
pads and supply pairs (V
in volume 2 of the Cyclone III Device Handbook.
AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5 V
REF
rail.
to ensure the device reliability when interfacing
REF
group when a voltage referenced input is used in
CCIO
CCIO
Cyclone III Device Datasheet: DC and
supply and prevent output switching
and GND). The restriction is in place to
Cyclone III Device I/O Features
CCIO
supply, there are restrictions
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