EP20K200EFC484-2XN Altera, EP20K200EFC484-2XN Datasheet - Page 68

• Manufacturer Part Number: EP20K200EFC484-2XN
• Description: IC APEX 20KE FPGA 200K 484-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K200EFC484-2XN

• Number Of Logic Elements/cells: 8320
• Number Of Labs/clbs: 832
• Total Ram Bits: 81920
• Number Of I /o: 376
• Number Of Gates: 404000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 200000
• Number Of Logic Blocks/elements: 8320
• # Registers: 52
• # I/os (max): 376
• Frequency (max): 205MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 8320
• Ram Bits: 106496
• Device System Gates: 526000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APEX 20K Programmable Logic Device Family Data Sheet
68
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum driver strength.
Figure 36
Figure 36. APEX 20K f
Figure 37
parameters can be used to estimate f
Quartus II software timing analysis should be used for more accurate
timing information.
shows the f
shows the f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ESBRC
ESBWC
ESBDATASU
ESBADDRSU
ESBDD
PD
PTERMCO
ESBWESU
ESBDATACO1
ESBDATACO2
PTERMSU
SU
H
CO
LUT
LE
MAX
ESB
MAX
MAX
Timing Model
timing model for APEX 20K devices.
timing model for APEX 20KE devices. These
MAX
for multiple levels of logic.
Routing Delay
t
t
t
F20+
F1—4
F5—20
Altera Corporation