EP20K160EFC484-1 Altera, EP20K160EFC484-1 Datasheet - Page 21

• Manufacturer Part Number: EP20K160EFC484-1
• Description: IC APEX 20KE FPGA 160K 484-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K160EFC484-1

• Number Of Logic Elements/cells: 6400
• Number Of Labs/clbs: 640
• Total Ram Bits: 81920
• Number Of I /o: 316
• Number Of Gates: 404000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
Figure 9. APEX 20K Interconnect Structure
Column
Interconnect
I/O
I/O
I/O
Row
Interconnect
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10
interconnect to drive LEs within MegaLAB structures.
MegaLAB
MegaLAB
MegaLAB
shows how the FastTrack Interconnect uses the local
I/O
I/O
APEX 20K Programmable Logic Device Family Data Sheet
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
I/O
I/O
I/O
Column
Interconnect
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