EPF10K100EFC484-1 Altera, EPF10K100EFC484-1 Datasheet - Page 15
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EPF10K100EFC484-1
Manufacturer Part Number
EPF10K100EFC484-1
Description
IC FLEX 10KE FPGA 100K 484-FBGA
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K100EFC484-1
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
338
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
FLEX 10KE
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
338
# I/os (max)
338
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1935
EPF10K100EFC484-1
EPF10K100EFC484-1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100EFC484-1
Manufacturer:
UNISONIC
Quantity:
9 000
Company:
Part Number:
EPF10K100EFC484-1N
Manufacturer:
AVAGO
Quantity:
11 350
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive write
enable, read enable, and clock enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write enable, read enable, clear, clock, and clock enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outputs (see
Figures 2
and 4). The column interconnect, which is adjacent
to the EAB, has twice as many channels as other columns in the device.
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the FLEX 10KE architecture, facilitating
efficient routing with optimum device utilization and high performance
(see
Figure
7).
Altera Corporation
15