EPF10K100EFC484-1 Altera, EPF10K100EFC484-1 Datasheet - Page 59
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EPF10K100EFC484-1
Manufacturer Part Number
EPF10K100EFC484-1
Description
IC FLEX 10KE FPGA 100K 484-FBGA
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K100EFC484-1
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
338
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
FLEX 10KE
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
338
# I/os (max)
338
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1935
EPF10K100EFC484-1
EPF10K100EFC484-1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100EFC484-1
Manufacturer:
UNISONIC
Quantity:
9 000
Company:
Part Number:
EPF10K100EFC484-1N
Manufacturer:
AVAGO
Quantity:
11 350
Altera Corporation
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t
t
t
t
t
t
t
t
t
t
t
t
t
EABAA
EABRCCOMB
EABRCREG
EABWP
EABWCCOMB
EABWCREG
EABDD
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWEH
EABWDSU
EABWDH
EABWASU
EABWAH
EABWO
Table 27. EAB Timing Macroparameters
Symbol
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Note (1)
Parameter
,
(6)
Conditions
59