EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 67
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EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2010 Altera Corporation
Configuration
Table 1–50
Table 1–50. Configuration Mode Specifications for Arria II Devices
JTAG Specifications
Table 1–51
devices.
Table 1–51. JTAG Timing Parameters and Values for Arria II Devices
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–52
and GZ devices.
Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices
Passive serial
Fast passive parallel
Fast active serial (fast clock)
Fast active serial (slow clock)
Remote update only in fast AS mode
t
t
t
t
t
t
t
t
t
Dev_CLRn
JCP
JCH
JCL
JPSU (TDI)
JPSU (TMS)
JPH
JPCO
JPZX
JPXZ
Symbol
lists the configuration mode specifications for Arria II GX and GZ devices.
lists the JTAG timing parameters and values for Arria II GX and GZ
lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX
TCK clock period
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Programming Mode
Description
Description
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
8.5
—
—
17
—
Min
500
DCLK Frequency
Min
30
14
14
—
—
—
1
3
5
Typ
—
—
26
13
—
Typ
—
Max
—
—
—
—
—
—
11
14
14
Max
125
125
40
20
10
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Unit
Unit
s
1–65