EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 78

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–76
Table 1–65. IOE Programmable Delay for Arria II GX Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Output
enable pin
delay
Delay from
output
register to
output pin
Input delay
from pin to
internal cell
Input delay
from pin to
input register
DQS bus to
input register
delay
Notes to
(1) The available setting for every delay chain starts with zero and ends with the specified maximum number of settings.
(2) The minimum offset represented in the table does not include intrinsic delay.
Parameter
Table
1–65:
Available
Settings
52
52
(1)
7
7
4
Table 1–64
Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices
IOE Programmable Delay
Table 1–65
chain for Arria II GX devices.
Output Duty Cycle
Note to
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
Minimum
Offset
Table
Symbol
(2)
0
0
0
0
0
lists the worst-case DCD specifications for Arria II GZ devices.
lists the delay associated with each supported IOE programmable delay
1–64:
0.413
0.339
1.494
1.493
0.074
I3
Fast Model
0.442
0.362
1.607
1.607
0.076
C4
Min
45
C3, I3
0.413
0.339
1.494
1.493
0.074
I5
Max
55
Maximum Offset
0.814
0.671
2.895
2.896
0.140
I3
Chapter 1: Device Datasheet for Arria II Devices
0.713
0.585
2.520
2.503
0.124
Min
C4
45
Slow Model
C4, I4
0.796
0.654
2.733
2.732
0.147
C5
December 2010 Altera Corporation
(Note 1)
Max
55
0.801
0.661
2.775
2.774
0.147
Switching Characteristics
I5
2.944
2.944
0.167
0.873
0.722
C6
Unit
%
Unit
ns
ns
ns
ns
ns