EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet
![IC CYCLONE IV FPGA 115K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP4CE115F29I8LN
Specifications of EP4CE115F29I8LN
Available stocks
Related parts for EP4CE115F29I8LN
EP4CE115F29I8LN Summary of contents
Page 1
... Therefore, commercial devices are indicated as C6, C7, C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8, or I8L. Automotive devices are indicated as A7. © December 2010 Altera Corporation 1. Cyclone IV Device Datasheet Cyclone IV FPGA Device Family Overview ...
Page 2
... Min Max Unit –0.5 1.8 V –0.5 3.75 V –0.5 1.8 V –0.5 3.9 V –0.5 3.9 V –0.5 2.625 V –0.5 2.625 V –0.5 1.8 V –0.5 3.95 V – –65 150 °C –40 125 °C Table 1–2 and © December 2010 Altera Corporation ...
Page 3
... I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device idle state, lifetimes are increased. Figure 1–1. Cyclone IV Devices Overshoot Duration © December 2010 Altera Corporation Condition (V) Overshoot Duration High Time ...
Page 4
... V 3.3 3.465 V 3 3.15 V 2.5 2.625 V 1.8 1.89 V 1.5 1.575 V 1.2 1.26 V 2.5 2.625 V 1.2 1.25 V 1.0 1.03 V — 3.6 V — CCIO — 85 °C — 100 °C — 125 °C — — — — © December 2010 Altera Corporation ...
Page 5
... Differential clock input pins power supply for 1 operation Differential clock input pins power supply for 1 operation V Transceiver output buffer power supply CCH_GXB Transceiver PMA and auxiliary power V CCA_GXB supply © December 2010 Altera Corporation (Note 1), (2) Conditions Min — — Conditions — — — — ...
Page 6
... I/O Banks 3, 8, and 9 where CCIO level of I/O CCIO located at I/O Banks 3B and 8B CC_CLKIN Table 1–6 lists the Unit ± 2000 V ± 1000 V ± 500 V ± 250 V © December 2010 Altera Corporation ...
Page 7
... IL –8 sustaining (minimum) current Bus hold low < V < V — IN CCIO overdrive current Bus hold high < V < V — IN CCIO overdrive current © December 2010 Altera Corporation (Note 1) (2) , Conditions Device — I CCIOMAX — CCIOMAX O - (Note 1)—Preliminary V (V) CCIO 1.5 1.8 ...
Page 8
... Unit Max Min Max Min Max 1.7 0.8 2 0.8 2 Unit Industrial and Automotive Max ±40 % ±40 % ±50 % ±50 % ±50 % Unit Industrial and Automotive Max ±10 % ±10 % ±10 % ±10 % ±10 % Equation 1–1 to determine the © December 2010 Altera Corporation V ...
Page 9
... Because R is negative (3.83/100 + 1) = 0.963 V Because R is positive 15.72/100 + 1 = 1.157 0.963 × 1.157 = 1.114 = 50 × 1.114 = 55.71 R final © December 2010 Altera Corporation dR/dT (%/°C) 0.262 0.234 0.219 0.199 0.161 (Note 1), (2), (3), (4), (5), (7) ( (|R |/100 + 1) ––––– ( ...
Page 10
... Typical – Typical – Quad Flat Quad Flat Fineline Unit Pack No Leads BGA (QFP) (QFN) (FBGA ( because of higher pin CO (Note 1) (Part 1 of 2)— Min Typ Max Unit k k k 108 k 163 k 19 143 351 k © December 2010 Altera Corporation ...
Page 11
... The I/O ramp rate more. For ramp rates faster than 10 ns, |IIOPIN dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. 1 During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF. © December 2010 Altera Corporation Conditions V = 3.3 V ± 5% (4) ...
Page 12
... CCIO 0. 0. CCIO CCIO 0. 0. CCIO CCIO 0 0 1.5 CCIO CCIO 0 0 1.5 CCIO CCIO “Glossary” on page 1–38. AN 447: Interfacing Cyclone III © December 2010 Altera Corporation CCIO (mA) –4 –2 –4 –0.1 –1 –2 –2 –2 –0.5 –0.5 ...
Page 13
... V + REF REF –0.15 Class II 0.08 0.08 f For more information about receiver input and transmitter output waveforms, and for other differential I/O standards, refer to the © December 2010 Altera Corporation V (V) REF Min Typ 1.19 1.25 0.833 0.9 0.85 0.9 0.71 ...
Page 14
... December 2010 Altera Corporation Max /2 + CCIO 0.125 /2 + CCIO 0.125 (V) DIF(AC) Max — — 0. CCIO V (V) (3) OS Typ Max — ...
Page 15
... For more information about power estimation tools, refer to the User Guide and the Handbook. © December 2010 Altera Corporation (Note 1) V (mV) V (V) (2) ...
Page 16
... Max 156.25 50 — 156. — — — — – 0.5% 2000 — — — ± 1% 125 10 — 125 — — 125 — 2.5/ 50 37.5 — 50 (1) 2 — — 2 © December 2010 Altera Corporation Unit MHz kHz — MHz MHz MHz ms ...
Page 17
... Clock data recovery (CDR) PPM tolerance (without — spread-spectrum clocking enabled) CDR PPM tolerance (with — spread-spectrum clocking enabled) Run length — © December 2010 Altera Corporation C6 C7 Min Typ Max Min Typ — 1 — — 1 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS 600 — ...
Page 18
... December 2010 Altera Corporation Unit µs µ Mbps Mbps mV — ...
Page 19
... Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode automatic mode (Figure 1–3). (12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. (13) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. © December 2010 Altera Corporation C6 C7 Min Typ Max ...
Page 20
... Two parallel clock cycles Output Status Signals 1 busy rx _ freqlocked Figure 1–4 shows the differential receiver input waveform. Cyclone IV Device Handbook, Volume LTD_Manual 3 t LTR_LTD_Manual ( LTD_Auto Chapter 1: Cyclone IV Device Datasheet Switching Characteristics 4 (2) 4 (1) © December 2010 Altera Corporation ...
Page 21
... V Setting, Tx Term = 100 —Preliminary Table 1–22. Typical V OD Symbol 1 V Typical (mV) 400 OD Note to Table 1–22: (1) This setting is required for compliance with the PCIe protocol. © December 2010 Altera Corporation (diff peak-peak (single-ended (diff peak-peak (single-ended for Tx term that equals 100 . ...
Page 22
... Switching Characteristics C8 Unit Min Typ Max — — 0.25 UI > 0.6 UI — — 0.14 UI — — 0.279 UI > 0.4 UI > 0.66 UI © December 2010 Altera Corporation ...
Page 23
... EP4CGX75 500 437.5 EP4CGX110 500 437.5 EP4CGX150 500 437.5 Note to Table 1–24: (1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. © December 2010 Altera Corporation Performance C8 C8L (1) C9L (1) 402 362 265 437.5 402 362 265 437 ...
Page 24
... December 2010 Altera Corporation Switching Characteristics “Glossary” on Typ Max Unit — 472.5 MHz — 362 MHz — 265 MHz — 325 MHz — ...
Page 25
... Table 1–27. Memory Block Performance Specifications for Cyclone IV Devices —Preliminary Memory Mode FIFO 256 × 36 Single-port 256 × 36 M9K Block Simple dual-port 256 × 36 CLK True dual port 512 × 18 single CLK © December 2010 Altera Corporation (Note 1), (2) (Part 2 of 2)—Preliminary Parameter 100 MHz) OUT ...
Page 26
... DCLK f Unit MAX 66 MHz 133 MHz 66 MHz 100 MHz Configuration and Remote MAX Unit MHz MHz (Note 1) (Part 1 of 2)—Preliminary Min Max Unit 40 — — — — — — ns — — — — — ns — — © December 2010 Altera Corporation ...
Page 27
... HSCLK (input clock ×4 10 — frequency) ×2 10 — ×1 10 — © December 2010 Altera Corporation Parameter “JTAG Waveform” of the External Memory Interfaces Handbook. Table 1–36 list the high-speed I/O timing for Cyclone IV devices. (Note 1), (2), C7, I7 C8, A7 Max Min Typ ...
Page 28
... Max 10 — — 72.5 10 — — 72.5 10 — — 72.5 10 — — 72.5 10 — — 72.5 10 — 170 10 — 145 © December 2010 Altera Corporation Unit Mbps Mbps Mbps Mbps Mbps Mbps — ps — Unit MHz MHz MHz MHz MHz MHz ...
Page 29
... Device ×7 70 — operation in ×4 40 — Mbps ×2 20 — ×1 10 — © December 2010 Altera Corporation C7, I7 C8, A7 Max Min Typ Max Min Typ Max Min 170 100 — 170 100 — 170 80 — 170 80 — 170 70 — ...
Page 30
... December 2010 Altera Corporation Unit Max 55 % 200 ps 700 ps — ps — Unit MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps % ...
Page 31
... Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades. © December 2010 Altera Corporation C7, I7 ...
Page 32
... December 2010 Altera Corporation Unit MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps ...
Page 33
... Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for Cyclone IV Devices (Note Symbol t OCTCAL Note to Table 1–39: (1) OCT calibration takes place after device configuration and before entering user mode. © December 2010 Altera Corporation of the External Memory Interface Handbook. Symbol t JIT(per) t JIT(cc) t JIT(duty) (Note ...
Page 34
... Max Offset Slow Corner Unit I8L C8L C9L I8L 1.921 3.389 4.146 3.412 ns 1.919 3.420 4.374 3.441 ns 0.623 1.160 1.420 1.168 ns 0.919 1.656 2.258 1.656 ns © December 2010 Altera Corporation ...
Page 35
... The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software. © December 2010 Altera Corporation Table 1–43 list the IOE programmable delay for Cyclone ...
Page 36
... Max Offset Slow Corner Unit 2.209 2.398 2.526 2.443 ns 2.205 2.406 2.563 2.450 ns 0.789 0.869 0.933 0.884 ns 1.225 1.407 1.562 1.421 ns © December 2010 Altera Corporation ...
Page 37
... The Quartus II timing analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after place-and-route is complete. f The Excel-based I/O Timing spreadsheet is downloadable from Literature website. © December 2010 Altera Corporation 1–37 Cyclone IV Devices Cyclone IV Device Handbook, Volume 3 ...
Page 38
... Cyclone IV Device Handbook, Volume 3 Definitions — — — — — JCP JPSU_TDI JPSU_TMS JCH JCL t t JPZX JPCO t t JSSU JSH JSZX JSCO — — — — — Chapter 1: Cyclone IV Device Datasheet Glossary REF JPH t JPXZ JSXZ © December 2010 Altera Corporation ...
Page 39
... Differential Waveform (Mathematical Function of Positive & Negative Channel) Receiver input High-speed I/O block: The total margin left after accounting for the sampling window and TCCS. skew margin RSKM = (TUI – SW – TCCS (RSKM) © December 2010 Altera Corporation Definitions Switchover INPFD ...
Page 40
... Delay from the PLL inclk pad to the I/O output register. Cyclone IV Device Handbook, Volume 3 Definitions REF V OL variation and clock skew. The clock is included in the TCCS measurement. CO Chapter 1: Cyclone IV Device Datasheet Glossary V CCIO IH(DC) V IL(DC) V IL( /w). C © December 2010 Altera Corporation ...
Page 41
... Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O Standards: Single-Ended Waveform Transmitter Output Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) t Signal low-to-high transition time (20–80%). RISE t Input register setup time — © December 2010 Altera Corporation Definitions — 1–41 Positive Channel ( Negative Channel ( Ground ...
Page 42
... AC differential input cross point voltage: The voltage at which the differential input signals must V X (AC) cross. W — X — Y — Z — Cyclone IV Device Handbook, Volume 3 Chapter 1: Cyclone IV Device Datasheet Definitions = ( must not exceed REF REF(DC) — — — — © December 2010 Altera Corporation Glossary = V – noise. The REF(AC) REF(DC) ...
Page 43
... February 2010 1.1 ■ November 2009 1.0 Initial release. © December 2010 Altera Corporation Changes Made Updated for the Quartus II software version 10.1 release. Updated Table 1–21 and Table 1–25. Minor text edits. Updated Table 1–3, Table 1–4, Table 1–21, Table 1–25, Table 1–28, Table 1–30, Table 1– ...
Page 44
... Cyclone IV Device Handbook, Volume 3 Chapter 1: Cyclone IV Device Datasheet Document Revision History © December 2010 Altera Corporation ...