EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 27
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EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Periphery Performance
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices
© December 2010 Altera Corporation
f
(input clock
frequency)
HSCLK
Symbol
f
1
Modes
×10
×8
×7
×4
×2
×1
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to
Performance Specifications
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Table 1–31
For definitions of high-speed timing specifications, refer to
t
Notes to
(1) For more information about JTAG waveforms, refer to
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time
Symbol
JSXZ
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
Min Typ Max Min Typ
10
10
10
10
10
10
Table
Update register valid output to high impedance
through
—
—
—
—
—
—
C6
1–30:
180
180
180
180
180
360
Table 1–36
10
10
10
10
10
10
of the External Memory Interfaces Handbook.
C7, I7
—
—
—
—
—
—
list the high-speed I/O timing for Cyclone IV devices.
Parameter
155.5
155.5
155.5
155.5
155.5
Max
311
Min
10
10
10
10
10
10
“JTAG Waveform”
C8, A7
(Note
Typ
—
—
—
—
—
—
1), (2),
155.5
155.5
155.5
155.5
155.5
Max
311
(Note 1)
in
(4)
Cyclone IV Device Handbook, Volume 3
“Glossary” on page
Min Typ
“Glossary” on page
10
10
10
10
10
10
(Part 1 of 2)—Preliminary
(Part 2 of 2)—Preliminary
Section III: System
C8L, I8L
—
—
—
—
—
—
Min
—
155.5
155.5
155.5
155.5
155.5
Max
311
1–38.
Max
25
Min Typ
10
10
10
10
10
10
1–38.
Unit
ns
1–27
—
—
—
—
—
—
C9L
132.5
132.5
132.5
132.5
132.5
Max
265
MHz
MHz
MHz
MHz
MHz
MHz
Unit