EP3C120F780I7 Altera, EP3C120F780I7 Datasheet - Page 31
![IC CYCLONE III FPGA 120K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C120F780I7
Manufacturer Part Number
EP3C120F780I7
Description
IC CYCLONE III FPGA 120K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780I7.pdf
(274 pages)
Specifications of EP3C120F780I7
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C120F780I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP3C120F780I7N
Manufacturer:
ALTERA
Quantity:
118
Design and Compilation
© November 2008 Altera Corporation
f
Figure 3. Synchronous Design
If the combinational logic output from your design feeds to another part of the design,
have the signal go through a register, as illustrated in
using the combinational logic output as a clock signal or as an asynchronous reset
signal. Due to propagation delays through the combinational logic, the signal may go
through a number of transitions before the output settles to a new value. This means
changes to the combinational output can trigger a period of instability.
As the input of the register is only sampled and transferred to the design (for
example, the combinational logic 2 shown in
clock, transitions taking place on data inputs of the register do not affect the register
output or input to the other part of the design until the next active clock edge. As long
as the setup and hold time of the register is not violated, the register effectively
isolates any glitches or instable input signals from other logics.
Figure 4. Registering Combinational Output Signal
It is recommended that you register the input signals to the device as well to filter out
any glitches. The Cyclone III I/Os have input registers for this purpose. Using the
input registers for your input signals allows faster setup times compared to using the
LE registers. This can be done with the Fast Input Register assignment.
Also, your design should not rely on delay paths within the architecture of a device,
for example using the LCELL primitives to increase the delay of certain signals in the
design because factors such as temperature, voltage, process change, or placement
and routing change could affect the timing of logic paths in the device. Any change in
timing to a specific path could cause unwanted functional changes and affect the
design functionality. Synchronization eliminates the unwanted functional changes.
For more information about synchronizing your design, refer to the
Recommendations for Altera Devices and the Quartus II Design Assistant
volume 1 of the Quartus II Handbook or the Quartus II Help.
Combinational
clock
Logic 1
clock
D
Q
D
Q
Figure
D
Combinational
4) on every active edge of the
Table
Logic 2
Q
4. This applies if you are
Design
chapter in
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