EP2S60F1020C4 Altera, EP2S60F1020C4 Datasheet - Page 229
EP2S60F1020C4
Manufacturer Part Number
EP2S60F1020C4
Description
IC STRATIX II FPGA 60K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F1020C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
718
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1131
EP2S60F1020C4ES
EP2S60F1020C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F1020C4N
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP2S60F1020C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Note to
(1)
f
f
f
t
f
f
f
f
t
f
t
t
t
t
I N
I N P F D
I N D U T Y
I N J I T T E R
V C O
O U T
O U T _ I O
S C A N C L K
C O N F I G P L L
C L B W
L O C K
P L L _ P S E R R
A R E S E T
A R E S E T _ R E C O N F I G
Table 5–93. Fast PLL Specifications
Limited by I/O f
Name
Table
5–93:
M A X
Input clock frequency (for -3 and -4 speed
grade devices)
Input clock frequency (for -5 speed grade
devices)
Input frequency to the PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤ 2 MHz
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 2 MHz
Upper VCO frequency range for –3 and –4
speed grades
Upper VCO frequency range for –5 speed
grades
Lower VCO frequency range for –3 and –4
speed grades
Lower VCO frequency range for –5 speed
grades
PLL output frequency to
PLL output frequency to LVDS or DPA clock
PLL clock output frequency to regular I/O
pin
Scanclk frequency
Time required to reconfigure scan chains
for fast PLLs
PLL closed-loop bandwidth
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
Accuracy of PLL phase shift
Minimum pulse width on
Minimum pulse width on the
when using PLL reconfiguration. Reset the
PLL after
. See
Table 5–77 on page 5–67
scandone
Description
goes high.
GCLK
areset
areset
for the maximum.
or
RCLK
signal.
signal
4.6875
4.6875
16.08
16.08
16.08
1.16
Min
300
300
150
150
150
500
40
10
Stratix II Device Handbook, Volume 1
75/f
DC & Switching Characteristics
S C A N C L K
5.00
0.03
Typ
0.5
1.0
1,040
1,040
28.00
Max
1.00
717
640
500
840
520
420
550
100
±15
(1)
60
ns (p-p)
ns (p-p)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ns
ps
ns
ns
%
5–93