EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 151
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EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Altera Corporation
February 2005
f
During switchover, the PLL VCO continues to run and either slows down
or speeds up, generating frequency drift on the PLL outputs. The clock
switchover transitions without any glitches. After the switch, there is a
finite resynchronization period to lock onto new clock as the VCO ramps
up. The exact amount of time it takes for the PLL to relock relates to the
PLL configuration and may be adjusted by using the programmable
bandwidth feature of the PLL. The preliminary specification for the
maximum time to relock is 100 µs.
For more information on clock switchover, see AN313: Implementing
Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change
Stratix GX device enhanced PLL counters and delay elements without
reloading a Programmer Object File (.pof). This provides considerable
flexibility for frequency synthesis, allowing real-time PLL frequency and
output clock delay variation. You can sweep the PLL output frequencies
and clock delay in prototype environments. The PLL reconfiguration
feature can also dynamically or intelligently control system clock speeds
or t
Clock delay elements at each PLL output port implement variable delay.
Figure 4–53
for the counters and the clock delay elements. The configuration time is
less than 20 μs for the enhanced PLL using a input shift clock rate of
25 MHz. The charge pump, loop filter components, and phase shifting
using VCO phase taps cannot be dynamically adjusted.
CO
requiring a system-controlled switchover between frequencies of
operation. You can use clkswitch together with the lock signal to
trigger the switch from a clock that is running but becomes unstable
and cannot be locked onto.
delays in end systems.
shows a diagram of the overall dynamic PLL control feature
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
4–85
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