EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 153
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Altera Corporation
February 2005
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). See
Figure 4–54. External Clock Outputs for PLLs 5 & 6
Notes to
(1)
(2)
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
e 0 Counter
e 1 Counter
e 2 Counter
e 3 Counter
Each external clock output pin can be used as a general purpose output pin from
the logic array. These pins are multiplexed with IOE outputs.
Two single-ended outputs are possible per output counter—either two outputs of
the same frequency and phase or one shifted 180°.
Figure
4–54:
4
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
Stratix GX Device Handbook, Volume 1
(2)
Figure
4–54.
Stratix GX Architecture
extclk0_a
extclk0_b
extclk1_a
extclk1_b
extclk2_a
extclk2_b
extclk3_a
extclk3_b
4–87
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