EP1SGX25FF1020C5 Altera, EP1SGX25FF1020C5 Datasheet - Page 47

• Manufacturer Part Number: EP1SGX25FF1020C5
• Description: IC STRATIX GX FPGA 25K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25FF1020C5

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 607
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 607
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Other
Transceiver
Features
Altera Corporation
June 2006
Notes to
(1)
(2)
IQ lines
Table 2–10. Possible Clocking Connections for Transceivers (Part 2 of 2)
REFCLKB from transceiver block 0 and transceiver block 4 does not drive the inter-transceiver lines or the GCLK
lines.
Inter-transceiver line 0 and inter-transceiver line 1 drive the transmitter PLL, while inter-transceiver line 2 drives
the receiver PLLs.
Source
Table
2–10:
Transmitter
v
PLL
(2)
Other important features of the Stratix GX transceivers are the power
down and reset capabilities, the external voltage reference and bias
circuitry, and hot swapping.
Individual Power-Down & Reset for the Transmitter & Receiver
Stratix GX transceivers offer a power saving advantage with their ability
to shut off functions that are not needed. The device can individually
reset the receiver and transmitter blocks and the PLLs. The Stratix GX
device can either globally power down and reset the transmitter and
receiver channels or do each channel separately.
connectivity between the reset signals and the Stratix GX logical blocks.
Receiver
v
PLL
(2)
GCLK
Destination
RCLK
Stratix GX Device Handbook, Volume 1
Table 2–11
FCLK
Stratix GX Transceivers
shows the
IQ Lines
2–37