EP1SGX25FF1020C5 Altera, EP1SGX25FF1020C5 Datasheet - Page 54

• Manufacturer Part Number: EP1SGX25FF1020C5
• Description: IC STRATIX GX FPGA 25K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25FF1020C5

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 607
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 607
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
Figure 3–3. Stratix GX High-Speed Interface Serialized in
Figure 3–4. Transmitter Timing Diagram
3–4
Stratix GX Device Handbook, Volume 1
Internal ×10 clock
Internal ×1 clock
TXLOADEN
data input
Receiver
Stratix GX
Logic Array
n – 1
The logic array sends parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logic array low-frequency clock’s
rising edge. The data is then transferred from the parallel register into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 3–3
channel and
and clocks in Stratix GX devices in
multiplier and J is the data parallelization division factor.
n – 0
Transmitter Circuit
shows the block diagram of a single SERDES transmitter
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD0
PD1
9
Figure 3–4
Fast
PLL
8
Register
Parallel
× W
TXLOADEN
7
shows the timing relationship between the data
×
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
10 Mode
6
5
Register
×
Serial
10 mode. W is the low-frequency
4
3
2
Altera Corporation
1
TXOUT+
TXOUT−
August 2005
0