EP1S60F1020C7 Altera, EP1S60F1020C7 Datasheet - Page 35
EP1S60F1020C7
Manufacturer Part Number
EP1S60F1020C7
Description
IC STRATIX FPGA 60K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S60F1020C7
Number Of Logic Elements/cells
57120
Number Of Labs/clbs
5712
Total Ram Bits
5215104
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1434
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S60F1020C7
Manufacturer:
ALTERA
Quantity:
846
Part Number:
EP1S60F1020C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S60F1020C7N
Manufacturer:
ALTERA
Quantity:
591
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TriMatrix
Memory
Altera Corporation
July 2005
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM blocks. Although these memory blocks are different, they
can all implement various types of memory with or without parity,
including true dual-port, simple dual-port, and single-port RAM, ROM,
and FIFO buffers.
RAM blocks.
Maximum
performance
True dual-port
memory
Simple dual-port
memory
Single-port memory
Shift register
ROM
FIFO buffer
Byte enable
Parity bits
Mixed clock mode
Memory initialization
Simple dual-port
memory mixed width
support
True dual-port
memory mixed width
support
Power-up conditions
Register clears
Mixed-port read-
during-write
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Table 2–3
Outputs cleared
Input and output
registers
Unknown
output/old data
M512 RAM Block
(32 × 18 Bits)
shows the size and features of the different
v
v
v
v
v
v
v
v
v
(1)
Stratix Device Handbook, Volume 1
Outputs cleared
Input and output
registers
Unknown
output/old data
M4K RAM Block
(128 × 36 Bits)
(1)
v
v
v
v
v
v
v
v
v
v
v
v
Stratix Architecture
unknown
Output registers
Unknown output
Outputs
(4K × 144 Bits)
M-RAM Block
(1)
v
v
v
(2)
v
v
v
v
v
v
2–21
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