EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 237

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
June 2006
Notes to
(1)
(2)
(3)
(4)
(5)
t
t
t
t
t
A N A L O G R E S E T P W
D I G I TA L R E S E T P W
T X _ P L L _ L O C K
R X _ F R E Q L O C K
R X _ F R E Q L O C K 2 P H A S E L O C K
Table 6–50. Stratix GX Transceiver Reset & PLL Lock Time Parameters
The minimum pulse width specified is associated with the power-down of circuits.
The clock recovery unit (CRU) phase locked-to-data time is based on a data rate of 500 Mbps and 8B/10B encoded
data.
After
reference clock.
After
There is no maximum pulse width specification. The GXB can be held in reset indefinitely.
Table
#pll_areset
#rx_analogreset
Symbol
(3)
6–50:
(4)
(5)
(5)
,
pll_enable
(2)
Routing delays vary depending on the load on a specific routing line. The
Quartus II software reports the routing delay information when running
the timing analysis for a design. Contact Altera Applications Engineering
for more details.
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
timing. All registers are within the IOE.
, the time for the CRU to switch to lock-to-data mode.
Figure 6–6
Min
, or PLL power-up, the time required for the transceiver PLL to lock to the
1
4
shows the timing model for bidirectional IOE pin
Typ
Stratix GX Device Handbook, Volume 1
DC & Switching Characteristics
Max
10
5
5
mS
Parallel clock
cycle
µS
mS
µS
Units
6–35