EP1SGX40DF1020C5N Altera, EP1SGX40DF1020C5N Datasheet - Page 54
EP1SGX40DF1020C5N
Manufacturer Part Number
EP1SGX40DF1020C5N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C5N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Introduction
Figure 3–3. Stratix GX High-Speed Interface Serialized in
Figure 3–4. Transmitter Timing Diagram
3–4
Stratix GX Device Handbook, Volume 1
Internal ×10 clock
Internal ×1 clock
TXLOADEN
data input
Receiver
Stratix GX
Logic Array
n – 1
The logic array sends parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logic array low-frequency clock’s
rising edge. The data is then transferred from the parallel register into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 3–3
channel and
and clocks in Stratix GX devices in
multiplier and J is the data parallelization division factor.
n – 0
Transmitter Circuit
shows the block diagram of a single SERDES transmitter
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD0
PD1
9
Figure 3–4
Fast
PLL
8
Register
Parallel
× W
TXLOADEN
7
shows the timing relationship between the data
×
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
10 Mode
6
5
Register
×
Serial
10 mode. W is the low-frequency
4
3
2
Altera Corporation
1
TXOUT+
TXOUT−
August 2005
0
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