EP2S130F1020C3N Altera, EP2S130F1020C3N Datasheet - Page 218

• Manufacturer Part Number: EP2S130F1020C3N
• Description: IC STRATIX II FPGA 130K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S130F1020C3N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 742
• Frequency (max): 778.82MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2159

Duty Cycle Distortion
5–82
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS/ HyperTransport
technology
Table 5–82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3
Devices
Row DDIO Output I/O
The information in
The DCD specification is based on a no logic array noise condition.
Standard
Table
Notes
5–82:
(1),
Table 5–82
(2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port
3.3 & 2.5 V
260
210
195
150
255
175
170
155
150
150
180
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is SSTL-2 and the DDIO output I/O standard is
SSTL-2 Class II, the maximum DCD is 60 ps (see
frequency is 267 MHz, the clock period T is:
Calculate the DCD as a percentage:
assumes the input clock has zero DCD.
TTL/CMOS
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
boundary)
boundary)
(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low
(T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high
1.8 & 1.5 V
380
330
315
265
370
295
290
275
270
270
180
(No PLL in Clock Path)
SSTL-2
2.5 V
145
100
140
180
85
85
65
60
55
60
55
1.8 & 1.5 V
SSTL/HSTL
145
100
140
180
85
85
65
60
50
60
55
Table
HyperTransport
Technology
LVDS/
3.3 V
Altera Corporation
110
120
105
180
5–82). If the clock
65
75
75
95
90
70
90
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps