EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 693
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Transmitter Channel-to-Channel Skew Optimization for Modes Other than
Basic (PMA Direct) Mode
High-speed serial clock and low-speed parallel clock skew between channels and
unequal latency in the transmitter phase compensation FIFO contribute to transmitter
channel-to-channel skew. Transmitter datapath clocking is set up to provide low
channel-to-channel skew when compared with non-bonded channel configurations.
■
■
In bonded channel configurations—the high-speed serial clock and low-speed
parallel clock for all bonded channels are generated by the CMU0 clock divider or
the ATX clock divider block, resulting in lower channel-to-channel clock skew.
The transmitter phase compensation FIFO in all bonded channels (except in Basic
[PMA Direct] ×N mode) share common pointers and control logic generated in the
central control unit (CCU), resulting in equal latency in the transmitter phase
compensation FIFO of all bonded channels. The lower transceiver clock skew and
equal latency in the transmitter phase compensation FIFOs in all channels
provides lower channel-to-channel skew in bonded channel configurations.
In non-bonded channel configurations—the high-speed serial clock and low-speed
parallel clock in each channel are generated independently by its local clock
divider. This results in higher channel-to-channel clock skew.
The transmitter phase compensation FIFO in each non-bonded channel (except in
Basic [PMA Direct] mode) has its own pointers and control logic that can result in
unequal latency in the transmitter phase compensation FIFO of each channel. The
higher transceiver clock skew and unequal latency in the transmitter phase
compensation FIFO in each channel can result in higher channel-to-channel skew.
Stratix IV Device Handbook Volume 2: Transceivers
2–21
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