EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 683

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Stratix IV Transceiver Clocking
FPGA Fabric PLLs-Transceiver PLLs Cascading
Figure 2–12. Input Reference Clocking Using Left and Right, Left, or Right PLL in VCO Bypass Mode
Notes to
(1) For more information, refer to
(2) For more information, refer to
(3) The green line represents the PLL cascade clock line and the blue lines represent 6G ATX PLL R1.
© March 2010 Altera Corporation
Figure
2–12:
For more information about configuring left or right PLLs in VCO bypass mode, refer
to
Bypass Mode” on page
“Configuration Example 4: Configuring Left and Right, Left, or Right PLL in VCO
“Transceiver Channel Datapath Clocking” on page
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional
Generation Logic)
Generation Logic)
(Transmitter Data
(Transmitter Data
FPGA Fabric
FPGA Fabric
FPGA CLK Pin
Dedicated
meet interface timing)
(VCO Bypass Mode)
(Phase Shift 45º to
PLL_R1
PLL_R2
(2)
2–78.
PLL Cascade
Clock Line
Reference
tx_clkout
Clock
Transceiver Block GXBR 3
Transceiver Block GXBR 2
Transceiver Block GXBR0
Transceiver Block GXBR1
ATX PLL Block R1 (6G)
ATX PLL Block R1 (6G)
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
2–20.
xN_Bottom (1)
Mode.
xN_Top (1)
Stratix IV Device Handbook Volume 2
(Note 3)
2–19