XC3S500E-4FGG320I Xilinx Inc, XC3S500E-4FGG320I Datasheet - Page 71
![IC FPGA SPARTAN-3E 500K 320-FBGA](/photos/6/72/67295/pk071-320_sml.jpg)
XC3S500E-4FGG320I
Manufacturer Part Number
XC3S500E-4FGG320I
Description
IC FPGA SPARTAN-3E 500K 320-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4FGG320I
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
232
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
320-BGA
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4FGG320I
Manufacturer:
SILICON
Quantity:
2 300
Company:
Part Number:
XC3S500E-4FGG320I
Manufacturer:
XILINX
Quantity:
8
Company:
Part Number:
XC3S500E-4FGG320I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4FGG320I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 49: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0]
The Configuration section provides detailed schematics for
each configuration mode. The schematics indicate the
required logic values for HSWAP, M[2:0], and VS[2:0] but do
not specify how the application provides the logic Low or
High value. The HSWAP, M[2:0], and VS[2:0] pins can be
either dedicated or reused by the FPGA application.
Dedicating the HSWAP, M[2:0], and VS[2:0] Pins
If the HSWAP, M[2:0], and VS[2:0] pins are not required by
the FPGA design after configuration, simply connect these
pins directly to the V
appropriate configuration schematic.
Reusing HSWAP, M[2:0], and VS[2:0] After Config-
uration
To reuse the HSWAP, M[2:0], and VS[2:0] pin after configu-
ration, use pull-up or pull-down resistors to define the logic
values shown in the appropriate configuration schematic.
The logic level on HSWAP dictates how to define the logic
levels on M[2:0] and VS[2:0], as shown in
application requires HSWAP to be High, the HSWAP pin is
DS312-2 (v3.8) August 26, 2009
Product Specification
HSWAP Value
0
1
R
Enabled
Disabled
during Configuration
I/O Pull-up Resistors
CCO
or GND supply rail shown in the
Table
Pulled High via an internal pull-up
resistor to the associated V
supply. No external pull-up
resistor is necessary.
Pulled High using a 3.3 to 4.7 kΩ
resistor to the associated V
supply.
49. If the
www.xilinx.com
Required Resistor Value to Define Logic Level on
High
pulled High using an external 3.3 to 4.7 kΩ resistor to
VCCO_0. If the application requires HSWAP to be Low dur-
ing configuration, then HSWAP is either connected to GND
or pulled Low using an appropriately sized external
pull-down resistor to GND. When HSWAP is Low, its pin has
an internal pull-up resistor to VCCO_0. The external
pull-down resistor must be strong enough to define a logic
Low on HSWAP for the I/O standard used during configura-
tion. For 2.5V or 3.3V I/O, the pull-down resistor is 560 Ω or
lower. For 1.8V I/O, the pull-down resistor is 1.1 kΩ or lower.
Once HSWAP is defined, use
values for M[2:0] and VS[2:0].
Use the weakest external pull-up or pull-down resistor value
allowed by the application. The resistor must be strong
enough to define a logic Low or High during configuration.
However, when driving the HSWAP, M[2:0], or VS[2:0] pins
after configuration, the output driver must be strong enough
to overcome the pull-up or pull-down resistor value and gen-
erate the appropriate logic levels. For example, to overcome
a 560 Ω pull-down resistor, a 3.3V FPGA I/O pin must use a
6 mA or stronger driver.
HSWAP, M[2:0], or VS[2:0]
CCO
CCO
Pulled Low using an appropriately sized
pull-down resistor to GND.
For a 2.5V or 3.3V interface: R < 560 Ω.
For a 1.8V interface: R < 1.1 kΩ.
Pulled Low using a 3.3 to 4.7 kΩ resistor
to GND.
Table 49
Functional Description
Low
to define the logic
71