XA3S700A-4FGG484Q Xilinx Inc, XA3S700A-4FGG484Q Datasheet - Page 52
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XA3S700A-4FGG484Q
Manufacturer Part Number
XA3S700A-4FGG484Q
Description
IC FPGA SPARTAN-3A 700K 484-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A XAr
Datasheet
1.XA3S200A-4FTG256I.pdf
(56 pages)
Specifications of XA3S700A-4FGG484Q
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Total Ram Bits
368640
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 125°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S700A-4FGG484Q
Manufacturer:
XILINX
Quantity:
455
Company:
Part Number:
XA3S700A-4FGG484Q
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XA3S700A-4FGG484Q
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Byte Peripheral Interface Configuration Timing
Table 53: Timing for BPI Configuration Mode
52
(Open-Drain)
T
T
T
T
T
T
T
T
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
Figure 14: Waveforms for BPI Configuration
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
New ConfigRate active
Minimum
T
CCLK1
Address
50
T
0
0
5
See TSMDCC in
CCO
DS681 (v1.1) February 3, 2009
Data
See
See
See
T
T
DCC
CCLKn
Address
Product Specification
Maximum
Table 45
Table 45
Table 49
–
–
5
–
Data
Table 50
DS529-3_05_121107
Address
T
cycles
Units
T
CCLK1
Data
CCD
ns
ns
ns
R