XC3SD1800A-5FGG676C Xilinx Inc, XC3SD1800A-5FGG676C Datasheet - Page 86
![SPARTAN-3ADSP FPGA 1800K 676FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3SD1800A-5FGG676C
Manufacturer Part Number
XC3SD1800A-5FGG676C
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-5FGG676C
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Total Ram Bits
1548288
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
XILINX
Quantity:
160
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS610 (v3.0) October 4, 2010
Product Specification
VCCINT
VCCINT
VCCINT VCCINT
VCCINT
VCCAUX
VCCO_2
VREF_0
L27N_2
L29N_2
L28N_2
L26N_0
L26P_0
INPUT
L24P_0
L24N_0
INPUT
L25N_0
L25P_0
L31P_2
L27P_2
GCLK0
GCLK1
L29P_2
GCLK3
L28P_2
GCLK2
GCLK7
GCLK6
GCLK5
GCLK4
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
14
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
VCCINT
VREF_0
AWAKE
INPUT
VREF_2
INPUT
INPUT
L35P_2
L31N_2
L34N_2
L34P_2
L30N_2
L30P_2
L32P_2
L32N_2
L23N_0
L23P_0
L22N_0
L20N_0
L20P_0
L16P_0
L16N_0
L35N_2
INIT_B
CSI_B
DOUT
MOSI
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
∇
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_2
VCCO_2
VCCO_0
VCCO_0
VREF_2
INPUT
L42P_2
INPUT
L38N_2
L38P_2
INPUT
L21N_0
L22P_0
L12P_0
L12N_0
L42N_2
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
16
I/O
I/O
I/O
I/O
I/O
∇
Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Right Half)
VCCINT
VCCAUX
VREF_2
VREF_0
INPUT
INPUT
INPUT
INPUT
L19N_0
L13N_0
L08N_0
INPUT
L55N_1
L39N_1
L27N_1
L17N_1
L46N_2
L46P_2
L43N_2
L43P_2
L33N_2
L33P_2
L19P_0
L21P_0
L13P_0
L08P_0
GND
GND
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A15
I/O
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
A7
VCCAUX
RHCLK6
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L08P_1
L47N_2
L47P_2
L36N_2
L36P_2
L18N_0
L18P_0
L17N_0
L17P_0
L57N_1
L55P_1
L47N_1
L39P_1
L34P_1
L27P_1
L17P_1
L12N_1
IRDY1
GND
A14
I/O
I/O
I/O
I/O
I/O
I/O
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
D1
D2
∇
∇
A6
Bank 0
VCCO_2
VCCO_0
VCCO_1
RHCLK7
VCCO_1
VREF_2
VREF_0
L08N_1
INPUT
INPUT
L40N_2
L40P_2
L37N_2
L37P_2
L15N_0
L15P_0
INPUT
L02N_0
L02P_0
L59P_1
L57P_1
L47P_1
L34N_1
L22P_1
L12P_1
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
Bank 2
SUSPEND
VREF_2
VREF_0
RHCLK1
INPUT
INPUT
L14N_0
L11N_0
INPUT
L01N_0
L59N_1
L53N_1
L42N_1
L30N_1
L22N_1
L14N_1
L10N_1
L04P_1
L01P_1
L41N_2
L41P_2
L39N_2
L39P_2
L14P_0
L11P_0
L01P_0
L64P_1
L53P_1
L42P_1
HDC
20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A24
I/O
I/O
I/O
I/O
A17
I/O
A16
I/O
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
I/O
I/O
∇
RHCLK0
L10P_1
L04N_1
L01N_1
DONE
L45N_2
L44N_2
L44P_2
L09N_0
L09P_0
L10N_0
L10P_0
L64N_1
L62N_1
L62P_1
L50N_1
L45P_1
L37N_1
L30P_1
L25P_1
L14P_1
LDC2
GND
GND
GND
GND
GND
GND
A25
A21
A20
I/O
I/O
I/O
I/O
I/O
I/O
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
VCCAUX
VCCAUX
VCCO_1
VCCAUX
VCCO_2
VCCO_0
VCCO_1
VCCO_1
VREF_2
VREF_1
L18N_1
INPUT
L07N_0
L05N_0
L05P_0
L58P_1
L58N_1
L49N_1
L46N_1
L50P_1
L45N_1
L37P_1
L25N_1
L21N_1
L13P_1
L09P_1
L45P_2
I/O
I/O
I/O
I/O
I/O
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
2
RHCLK4
VREF_1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L21P_1
L18P_1
L13N_1
L09N_1
L07P_1
L03P_1
L48N_2
L48P_2
L07P_0
L06N_0
L06P_0
L56N_1
L51P_1
L48P_1
L49P_1
L46P_1
L40N_1
L38N_1
L36N_1
L33P_1
L28P_1
L26P_1
L23P_1
TDO
A13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
23
∇
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A0
∇
∇
A4
DIN/MISO
www.xilinx.com
RHCLK5
VREF_1
INPUT
INPUT
INPUT
INPUT
INPUT
VREF_1
INPUT
VREF_1
L19P_1
L15P_1
L11P_1
L07N_1
L03N_1
L52N_2
L61N_1
L56P_1
L54N_1
L51N_1
L48N_1
L40P_1
L38P_1
L36P_1
L33N_1
L28N_1
L26N_1
L23N_1
L52P_2
GND
GND
CCLK
GND
GND
GND
A12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1
D0
∇
∇
∇
A5
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VREF_1
RHCLK3
L19N_1
INPUT
L15N_1
L11N_1
L05N_1
L02N_1
L51N_2
INPUT
L65N_1
L63N_1
L61P_1
L54P_1
L52N_1
INPUT
L44N_1
L43N_1
L41P_1
L35N_1
INPUT
L32N_1
L31N_1
L29P_1
INPUT
L24P_1
L16P_1
L51P_2
INPUT
TRDY1
LDC0
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
25
I/O
A23
I/O
I/O
I/O
A19
I/O
I/O
A11
I/O
I/O
∇
∇
∇
A8
∇
∇
VREF_1
VREF_1
RHCLK2
VREF_1
VREF_1
INPUT
INPUT
INPUT
INPUT
L20N_1
L20P_1
L16N_1
L06N_1
L06P_1
L05P_1
L02P_1
INPUT
L65P_1
L63P_1
L60N_1
L60P_1
L52P_1
INPUT
L44P_1
L43P_1
L41N_1
L35P_1
L32P_1
L31P_1
L29N_1
INPUT
L24N_1
INPUT
GND
LDC1
GND
GND
GND
GND
GND
A22
A18
A10
I/O
I/O
I/O
I/O
I/O
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
A9
∇
∇
∇
∇
Spartan-3A DSP FPGA Family: Pinout Descriptions
W
G
M
V
Y
A
A
A
B
A
C
A
D
A
E
A
F
A
B
C
D
E
F
H
J
K
L
N
P
R
T
U
Right Half of FG676
Package (Top View)
86