XC6SLX45-3FGG676I Xilinx Inc, XC6SLX45-3FGG676I Datasheet - Page 11

• Manufacturer Part Number: XC6SLX45-3FGG676I
• Description: IC FPGA SPARTAN 6 43K 676FGGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX45-3FGG676I

• Number Of Logic Elements/cells: 43661
• Number Of Labs/clbs: 3411
• Total Ram Bits: 2138112
• Number Of I /o: 358
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

eFUSE Read Endurance
Table 11
more information, see the Spartan-6 FPGA Configuration User Guide.
Table 11: eFUSE Read Endurance
GTP Transceiver Specifications
GTP transceivers are available in the Spartan-6 LXT family of devices. See DS160: Spartan-6 Family Overview for more
information.
GTP Transceiver DC Characteristics
Table 12: Absolute Maximum Ratings for GTP Transceivers
Table 13: Recommended Operating Conditions for GTP Transceivers
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
Notes:
1.
2.
3.
DNA_CYCLES
AES_CYCLES
MGTAVTTRCAL
MGTAVTTRCAL
MGTAVCCPLL
MGTAVCCPLL
MGTAVTTTX
MGTAVTTRX
MGTAVTTRX
MGTAVTTTX
V
MGTAVCC
MGTAVCC
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Each voltage listed requires the filter circuit described in Spartan-6 FPGA GTP Transceivers User Guide.
Voltages are specified for the temperature range of T
The voltage level of MGTAVCCPLL must not exceed the voltage level of MGTAVCC +10mV. The voltage level of MGTAVCC must not exceed the
voltage level of MGTAVCCPLL.
MGTREFCLK
Symbol
Symbol
Symbol
V
IN
lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For
Analog supply voltage for the GTP transmitter and receiver circuits relative to GND
Analog supply voltage for the GTP transmitter termination circuit relative to GND
Analog supply voltage for the GTP receiver termination circuit relative to GND
Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to
GND
Analog supply voltage for the resistor calibration circuit of the GTP transceiver
bank (top or bottom)
Analog supply voltage for the GTP transmitter and receiver circuits relative to
GND
Analog supply voltage for the GTP transmitter termination circuit relative to GND
Analog supply voltage for the GTP receiver termination circuit relative to GND
Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to
GND
Analog supply voltage for the resistor calibration circuit of the GTP transceiver
bank (top or bottom)
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
Reference clock absolute input voltage
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
Number of JTAG FUSE_KEY or FUSE_CNTL read command operations.
Unaffected by SHIFT operations.
j
Description
= –40C to +100C.
Description
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
(1)
(1)(2)(3)
-3
Speed Grade
1.14
1.14
1.14
1.14
1.14
Min
-3N
30,000,000
30,000,000
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MIn
1.20
1.20
1.20
1.20
1.20
Typ
-2
Max
1.32
1.32
1.32
1.32
1.32
1.32
1.32
-1L
Max
1.26
1.26
1.26
1.26
1.26
Cycles
Cycles
Units
(Min)
Read
Read
Units
Units
V
V
V
V
V
V
V
V
V
V
V
V
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