XC6SLX45-3FGG676I Xilinx Inc, XC6SLX45-3FGG676I Datasheet - Page 56

• Manufacturer Part Number: XC6SLX45-3FGG676I
• Description: IC FPGA SPARTAN 6 43K 676FGGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX45-3FGG676I

• Number Of Logic Elements/cells: 43661
• Number Of Labs/clbs: 3411
• Total Ram Bits: 2138112
• Number Of I /o: 358
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 57: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode
Table 58: Miscellaneous DCM Timing Parameters
Table 59: Frequency Synthesis
Table 60: DCM Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
Notes:
1.
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
DCM_RST_PW_MIN
CLKFX_MULTIPLY (DCM_SP)
CLKFX_DIVIDE (DCM_SP)
CLKDV_DIVIDE (DCM_SP)
CLKFX_MULTIPLY (DCM_CLKGEN)
CLKFX_DIVIDE (DCM_CLKGEN)
CLKFXDV_DIVIDE (DCM_CLKGEN)
T
T
T
DMCCK_PSEN
DMCCK_PSINCDEC
DMCKO_PSDONE
The values in this table are based on the operating conditions described in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT
attribute is set to 0.
The DCM_DELAY_STEP values are provided at the end of
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM
DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected.
Symbol
Symbol
(2)
/ T
DMCKC_PSEN
/ T
DMCKC_PSINCDEC
Symbol
Attribute
When CLKIN < 60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
When CLKIN  60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
Minimum guaranteed delay for variable phase
shifting.
Maximum guaranteed delay for variable phase
shifting
Minimum duration of a RST pulse width
Description
Table
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
(1)
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
52.
Description
Description
Table 51
and
±(INTEGER(10 x (TCLKIN – 3 ns)))
±(INTEGER(15 x (TCLKIN – 3 ns)))
±(MAX_STEPS x DCM_DELAY_STEP_MIN)
±(MAX_STEPS x DCM_DELAY_STEP_MAX)
Min
1.5
Table
2
1
2
1
2
56.
Amount of Phase Shift
1.50
0.00
1.50
0.00
1.50
-3
(1)
Speed Grade
1.50
0.00
1.50
0.00
1.50
-3N
Min
3
1.50
0.00
1.50
0.00
1.50
-2
Max
–
Max
256
256
32
32
16
32
CLKIN cycles
1.50
0.00
1.50
0.00
1.50
-1L
Units
Units
steps
steps
Units
ps
ps
ns
ns
ns
56