XC5VLX20T-1FFG323C Xilinx Inc, XC5VLX20T-1FFG323C Datasheet - Page 42
![IC FPGA VIRTEX-5LX 20K 323-FCBGA](/photos/19/4/190421/4579315_sml.jpg)
XC5VLX20T-1FFG323C
Manufacturer Part Number
XC5VLX20T-1FFG323C
Description
IC FPGA VIRTEX-5LX 20K 323-FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Specifications of XC5VLX20T-1FFG323C
Total Ram Bits
958464
Number Of Logic Elements/cells
19968
Number Of Labs/clbs
1560
Number Of I /o
172
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
323-BBGA, FCBGA
No. Of Logic Blocks
3120
No. Of Gates
20000
No. Of Macrocells
3120
No. Of Speed Grades
1
No. Of I/o's
172
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX20T-1FFG323C
Manufacturer:
XILINX
Quantity:
201
Company:
Part Number:
XC5VLX20T-1FFG323C
Manufacturer:
XILINX
Quantity:
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Company:
Part Number:
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Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX20T-1FFG323C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Input Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Setup/Hold for Control Lines
T
T
T
Setup/Hold for Data Lines
T
T
T
T
T
Sequential Delays
T
Propagation Delays
T
ISCCK_BITSLIP
ISCCK_CE
ISCCK_CE2
ISDCK_D
ISDCK_DDLY
ISDCK_DDR
ISDCK_DDLY_DDR
ISCKD_DDLY_DDR
ISCKO_Q
ISDO_DO
Recorded at 0 tap value.
T
ISCCK_CE2
/T
/ T
ISCKD_D
Symbol
/ T
/T
/T
ISCKC_CE
ISCKD_DDR
/ T
ISCKC_CE2
ISCKD_DDLY
and T
ISCKC_BITSLIP
ISCKC_CE2
(2)
(2)
are reported as T
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK (for CE1)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
D pin Setup/Hold with respect to CLK
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
D pin Setup/Hold with respect to CLK at DDR mode
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)
CLKDIV to out at Q pin
D input to DO output pin
ISCCK_CE
/T
Description
ISCKC_CE
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
in TRACE report.
–0.24
–0.12
–0.09
–0.12
–0.09
0.10
0.00
0.43
0.03
0.11
0.34
0.31
0.34
0.31
0.46
0.20
-3
Speed Grade
–0.24
–0.12
–0.09
–0.12
–0.09
0.11
0.00
0.49
0.04
0.13
0.37
0.33
0.37
0.33
0.51
0.22
-2
–0.24
–0.12
–0.08
–0.12
–0.08
0.12
0.00
0.59
0.06
0.15
0.39
0.36
0.39
0.36
0.60
0.26
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
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