XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 28

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Input Serializer/Deserializer Switching Characteristics
Table 34: ISERDES Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
Setup/Hold for Control Lines
Setup/Hold for Data Lines
Sequential Delays
Propagation Delays
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Recorded at 0 tap value. Refer to Timing Report for other values.
T
ISCCK_BITSLIP
ISCCK_CE
ISCCK_CE2
ISCCK_DLYCE
ISCCK_DLYINC
ISCCK_DLYRST
ISCCK_SR
ISDCK_D
ISDCK_DDR
ISCKO_Q
ISDO_DO_IOBDELAY_IFD
ISDO_DO_IOBDELAY_NONE
ISDO_DO_IOBDELAY_BOTH
ISDO_DO_IOBDELAY_IBUF
ISCCK_CE2
/
/
T
Symbol
and T
T
/
ISCKD_D
/
T
ISCKC_CE
T
/
ISCKC_CE2
/
ISCKD_DDR
/
T
/
T
T
T
ISCKC_DLYCE
ISCKC_CE2
ISCKC_DLYINC
ISCKC_BITSLIP
ISCKC_DLYRST
(2)
(2)
are reported as T
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK (for CE1)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
DLYCE pin Setup/Hold with respect to CLKDIV
DLYINC pin Setup/Hold with respect to CLKDIV
DLYRST pin Setup/Hold with respect to CLKDIV
SR pin Setup with respect to CLKDIV
D pin Setup/Hold with respect to CLK
(IOBDELAY = IBUF or NONE)
D pin Setup/Hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin Setup/Hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE)
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
CLKDIV to out at Q pin
D input to DO output pin (IOBDELAY = IFD)
D input to DO output pin (IOBDELAY = NONE)
D input to DO output pin (IOBDELAY = BOTH,
IOBDELAY_TYPE = DEFAULT)
D input to DO output pin
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D input to DO output pin (IOBDELAY = IBUF,
IOBDELAY_TYPE = DEFAULT)
D input to DO output pin
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
ISCCK_CE
/
T
ISCKC_CE
Description
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(1)
(1)
in TRCE report.
(IOBDELAY = BOTH,
(IOBDELAY = IBUF,
(1)
(1)
–0.20
–0.37
–0.04
–0.03
–0.11
–6.51
–0.68
–0.11
–6.51
–0.68
0.28
0.48
0.11
0.16
0.11
0.01
0.36
0.37
0.64
0.24
6.64
0.81
0.24
6.64
0.81
0.59
0.17
0.17
6.00
0.74
6.00
0.74
-12
Speed Grade
–0.16
–0.30
–0.03
–0.02
–0.11
–6.51
–0.68
–0.11
–6.51
–0.68
0.34
0.57
0.14
0.19
0.13
0.01
0.43
0.45
0.77
0.28
7.63
0.87
0.28
7.63
0.87
0.71
0.20
0.20
6.91
0.79
6.91
0.79
-11
–0.13
–0.25
–0.02
–0.02
–0.11
–6.51
–0.68
–0.11
–6.51
–0.68
0.40
0.69
0.16
0.23
0.16
0.01
0.51
0.54
0.92
0.34
8.84
1.08
0.34
8.84
1.08
0.85
0.24
0.24
7.96
0.99
7.96
0.99
-10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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