XC5VLX50-2FFG676C Xilinx Inc, XC5VLX50-2FFG676C Datasheet - Page 191
![IC FPGA VIRTEX-5 50K 676-FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-2FFG676C
Manufacturer Part Number
XC5VLX50-2FFG676C
Description
IC FPGA VIRTEX-5 50K 676-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-2FFG676C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Company:
Part Number:
XC5VLX50-2FFG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
or flip-flop is available to implement a synchronous read. In this case, the clock-to-out of
the flip-flop determines the overall delay and improves performance. However, one
additional cycle of clock latency is added. Any of the 32 bits can be read out
asynchronously (at the O6 LUT outputs) by varying the 5-bit address. This capability is
useful in creating smaller shift registers (less than 32 bits). For example, when building a
13-bit shift register, simply set the address to the 13
diagram of a 32-bit shift register.
X-Ref Target - Figure 5-15
Figure 5-16
generator.
X-Ref Target - Figure 5-16
SHIFTIN (D)
Address (A[4:0])
illustrates an example shift register configuration occupying one function
SHIFTIN (D)
SHIFTIN (MC31 of Previous LUT)
A[4:0]
CLK
CE
CLK
WE
Figure 5-15: 32-bit Shift Register Configuration
Figure 5-16: Representation of a Shift Register
(AX)
www.xilinx.com
5
(WE/CE)
(A[6:2])
(CLK)
5
32-bit Shift Register
DI1
A[6:2]
CLK
CE
SRLC32E
MUX
Q
SRL32
MC31
O6
th
bit.
Figure 5-15
SHIFTOUT (Q31)
D Q
SHIFTOUT(Q31)
(AQ)
UG190_5_16_050506
(Optional)
is a logic block
ug190_5_15_050506
Output (Q)
Registered
Output
CLB Overview
191
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