XC5VLX50-2FFG676C Xilinx Inc, XC5VLX50-2FFG676C Datasheet - Page 75
![IC FPGA VIRTEX-5 50K 676-FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-2FFG676C
Manufacturer Part Number
XC5VLX50-2FFG676C
Description
IC FPGA VIRTEX-5 50K 676-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-2FFG676C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-2FFG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Application Examples
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Standard Usage
Board-Level Clock Generation
The Virtex-5 FPGA DCM can be used in a variety of creative and useful applications. The
following examples show some of the more common applications.
The circuit in
access to RST and LOCKED pins. This example shows the simplest use case for a DCM.
X-Ref Target - Figure 2-8
The board-level clock generation example in
generate output clocks for other components on the board. This clock can then be used to
interface with other devices. In this example, a DDR register is used with its inputs
connected to GND and V
stays within global routing until it reaches the output register. The quality of the clock is
maintained.
The board-level clock generation example in
the clock generation for a forwarded clock on the board.
Figure 2-8
IBUFG
IBUF
shows DCM_BASE implemented with internal feedback and
CC
www.xilinx.com
. Because the output of the DCM is routed to BUFG, the clock
Figure 2-8: Standard Usage
CLKIN
CLKFB
RST
DCM_BASE
Figure
Figure 2-9
2-10, with internal feedback, illustrates
CLKFX180
CLK2X180
LOCKED
CLK180
CLK270
CLKDV
CLKFX
illustrates how to use a DCM to
CLK2X
CLK90
CLK0
Application Examples
ug190_2_08_032506
BUFG
OBUF
75
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