XC5VLX50-3FFG676C Xilinx Inc, XC5VLX50-3FFG676C Datasheet - Page 169
![IC FPGA VIRTEX-5 50K 676-FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-3FFG676C
Manufacturer Part Number
XC5VLX50-3FFG676C
Description
IC FPGA VIRTEX-5 50K 676-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-3FFG676C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
122-1582
XC5VLX50-3FFG676C
XC5VLX50-3FFG676C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-3FFG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 4-25: Block RAM ECC Mode Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Setup and Hold Relative to Clock (CLK)
Clock to Out Delays
(Standard ECC Mode)
(Standard ECC Mode)
(Encode-only Mode)
(Encode-only Mode)
(register mode)
T
T
T
T
(latch mode)
RDCK_DI_ECC
RCKD_DI_ECC
RDCK_DI_ECC
RCKD_DI_ECC
Parameter
T
T
RCKO_DO
RCKO_DO
Block RAM ECC Mode Timing Parameters
T
Encode-Only ECC Write Timing
Encode-Only ECC Read Timing
Decode-Only ECC Write Timing
Decode-Only ECC Read Timing
RxCK_x
•
•
•
•
•
•
Table 4-25
= Setup time (before clock edge) and T
Clock to Output
Clock to Output
Setup/hold time for WREN and WRADDR are the same as standard ECC.
At time TRDCK_DI_ECC (encode-only ECC), before time T1W, write data A (hex)
becomes valid at the DI[63:0] inputs of the block RAM.
At time TRCKO_ECC_PARITY (encode-only ECC), after time T1W, ECC parity data
PA (hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.
Encode-only ECC read timing are the same as normal block RAM read timing.
Decode-only ECC write timing is the same as normal block RAM write timing.
Decode-only ECC read timing is the same as standard ECC read timing.
Data inputs
Data inputs
Function
shows the Virtex-5 FPGA block RAM ECC mode timing parameters.
(1)
(1)
(2)
(2)
CLK to DO
CLK to DO
Control
Signal
www.xilinx.com
DI
DI
(Figure
Time before the clock that data must be stable at the DI
inputs of the block RAM. Standard ECC mode.
Time after the clock that data must be stable at the DI
inputs of the block RAM. Standard ECC mode.
Time before the clock that data must be stable at the DI
inputs of the block RAM. Encode-only mode.
Time after the clock that data must be stable at the DI
inputs of the block RAM. Encode-only mode.
Time after the clock that the output data is stable at the
DO outputs of the block RAM (without output
register).
Time after the clock that the output data is stable at the
DO outputs of the block RAM (with output register).
RCKx_x
= Hold time (after clock edge)
4-31)
Description
Built-in Error Correction
169
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