XC5VLX50-3FFG676C Xilinx Inc, XC5VLX50-3FFG676C Datasheet - Page 338
![IC FPGA VIRTEX-5 50K 676-FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-3FFG676C
Manufacturer Part Number
XC5VLX50-3FFG676C
Description
IC FPGA VIRTEX-5 50K 676-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-3FFG676C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
122-1582
XC5VLX50-3FFG676C
XC5VLX50-3FFG676C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-3FFG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
338
IDELAYCTRL Primitive
IDELAYCTRL Ports
Figure 7-15
X-Ref Target - Figure 7-15
RST - Reset
The reset input pin (RST) is an active-High asynchronous reset. IDELAYCTRL must be
reset after configuration (and the REFCLK signal has stabilized) to ensure proper
IODELAY operation. A reset pulse width T
must be reset after configuration.
REFCLK - Reference Clock
The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all
IODELAY modules in the same region. This clock must be driven by a global clock buffer
(BUFGCTRL). REFCLK must be F
(IDELAYCTRL_REF_PRECISION) to guarantee a specified IODELAY resolution
(T
PLL, or from the DCM, and must be routed on a global clock buffer.
RDY - Ready
The ready (RDY) signal indicates when the IODELAY modules in the specific region are
calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock
period or more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. The
implementation tools allow RDY to be unconnected/ignored.
timing relationship between RDY and RST.
IDELAYRESOLUTION
shows the IDELAYCTRL primitive.
). REFCLK can be supplied directly from a user-supplied source, the
Figure 7-15: IDELAYCTRL Primitive
www.xilinx.com
IDELAYCTRL_REF
REFCLK
RST
IDELAYCTRL
IDELAYCTRL_RPW
ug190_7_10_041206
RDY
± the specified ppm tolerance
is required. IDELAYCTRL
Figure 7-16
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
illustrates the
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