XC5VSX50T-1FFG665C Xilinx Inc, XC5VSX50T-1FFG665C Datasheet - Page 331

• Manufacturer Part Number: XC5VSX50T-1FFG665C
• Description: IC FPGA VIRTEX-5 50K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665C

• Total Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 8160
• No. Of Gates: 50000
• Family Type: Virtex-5 SXT
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1568

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Stability after an Increment/Decrement Operation
IODELAY VHDL and Verilog Instantiation Template
Clock Event 1
On the rising edge of C, a reset is detected, causing the output DATAOUT to select tap 0 as
the output from the 64-tap chain (assuming IDELAY_VALUE = 0).
Clock Event 2
A pulse on CE and INC is captured on the rising edge of C. This indicates an increment
operation. The output changes without glitches from tap 0 to tap 1. See
Increment/Decrement
Clock Event 3
CE and INC are no longer asserted, thus completing the increment operation. The output
remains at tap 1 indefinitely until there is further activity on the RST, CE, or INC pins.
Figure 7-9
another. Clearly, when the data value at tap 0 is different from the data value at tap 1, the
output must change state. However, when the data values at tap 0 and tap 1 are the same
(e.g., both 0 or both 1), then the transition from tap 0 to tap 1 causes no glitch or disruption
on the output. This concept can be comprehended by imagining the receiver data signal in
the IODELAY tap chain. If tap 0 and tap 1 are both near the center of the receiver data eye,
then the data sampled at tap 0 should be no different than the data sampled at tap 1. In this
case, the transition from tap 0 to tap 1 causes no change to the output. To ensure that this is
the case, the increment/decrement operation of IODELAY is designed to be glitchless.
The user can dynamically adjust the IODELAY tap setting in real-time while live user data
is passing through the IODELAY element; the adjustments do not disrupt the live user
data.
The glitchless behavior also applies when an IODELAY element is used in the path of a
clock signal. Adjusting the tap setting does not cause a glitch or disruption on the output.
The tap setting of the IODELAY element in the clock path can be adjusted without
disrupting state machines that could be running on that clock.
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signals names.
Fixed Delay Mode
The Libraries Guide includes templates showing how to instantiate the IODELAY module
in fixed delay mode with a tap setting of 31. IDELAYCTRL must also be instantiated when
operating in this mode. See
Variable Delay Mode
The Libraries Guide shows how to instantiate the IODELAY module in variable delay
mode. IDELAYCTRL must also be instantiated when operating in this mode. See
IDELAYCTRL Overview, page
shows a period of instability when the output is changing from one tap to
Operation.
www.xilinx.com
IDELAYCTRL Overview, page
337.
Input/Output Delay Element (IODELAY)
337.
Stability after an
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