XC5VLX110T-1FFG1136C Xilinx Inc, XC5VLX110T-1FFG1136C Datasheet - Page 144

• Manufacturer Part Number: XC5VLX110T-1FFG1136C
• Description: IC FPGA VIRTEX-5 110K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-1FFG1136C

• Total Ram Bits: 5455872
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 640
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Gates: 110000
• Family Type: Virtex-5 LXT
• No. Of Speed Grades: 1
• No. Of I/o's: 640
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 4: Block RAM
FIFO Operations
144
Reset
Operating Mode
Standard Mode
First Word Fall Through (FWFT) Mode
Table 4-15: FIFO I/O Port Names and Descriptions (Continued)
Reset is an asynchronous signal for both multirate and synchronous FIFO. Reset must be
asserted for three cycles to reset all read and write address counters and initialize flags
after power up. Reset does not clear the memory, nor does it clear the output register.
When reset is asserted High, EMPTY and ALMOST_EMPTY will be set to 1, FULL and
ALMOST_FULL will be reset to 0. The reset signal must be High for at least three read
clock and write clock cycles to ensure all internal states are reset to the correct values.
During RESET, RDEN and WREN must be held Low.
There are two operating modes in FIFO functions. They differ only in output behavior
immediately after the first word is written to a previously empty FIFO.
After the first word is written into an empty FIFO, the Empty flag deasserts synchronously
with RDCLK. After Empty is deasserted Low and RDEN is asserted, the first word will
appear at DO on the rising edge of RDCLK.
After the first word is written into an empty FIFO, this word automatically appears at DO
before RDEN is asserted. Subsequent Read operations require Empty to be Low and RDEN
to be High.
ALMOSTEMPTY
RDCOUNT
WRCOUNT
WRERR
RDERR
Port Name
Figure 4-20
Direction
Output
Output
Output
Output
Output
illustrates the difference between standard mode and FWFT mode.
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Almost all valid entries in FIFO have been read.
Synchronous with RDCLK. The offset for this flag is user
configurable. See
deassertion.
The FIFO data read pointer. It is synchronous with RDCLK.
The value will wrap around if the maximum read pointer
value has been reached.
The FIFO data write pointer. It is synchronous with WRCLK.
The value will wrap around if the maximum write pointer
value has been reached.
When the FIFO is full, any additional write operation
generates an error flag. Synchronous with WRCLK.
When the FIFO is empty, any additional read operation
generates an error flag. Synchronous with RDCLK.
Table 4-16
Description
for the clock latency for flag
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010