XC4VFX100-11FFG1152C Xilinx Inc, XC4VFX100-11FFG1152C Datasheet - Page 205
XC4VFX100-11FFG1152C
Manufacturer Part Number
XC4VFX100-11FFG1152C
Description
IC FPGA VIRTEX-4FX 100K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX100-11FFG1152C
Number Of Logic Elements/cells
94896
Number Of Labs/clbs
10544
Total Ram Bits
6930432
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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XC4VFX100-11FFG1152C
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Table 5-5: General Slice Timing Parameters
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Combinatorial Delays
T
T
T
ILO
IF5
IF5X
Parameter
General Slice Timing Model and Parameters
R
Timing Parameters
F/G inputs to X/Y outputs
F/G inputs to F5 output
F/G inputs to XMUX output
A simplified Virtex-4 FPGA slice is shown in
FPGA slice are omitted for clarity. Only the elements relevant to the timing paths described
in this section are shown.
Table 5-5
Figure
Function
inputs
inputs
FXINA
FXINB
5-20.
CLK
G
BY
BX
CE
SR
F
shows the general slice timing parameters for a majority of the paths in
Figure 5-20: Simplified Virtex-4 FPGA General SLICEL/SLICEM
LUT
LUT
Propagation delay from the F/G inputs of the slice, through the look-
up tables (LUTs), to the X/Y outputs of the slice.
Propagation delay from the F/G inputs of the slice, through the LUTs
and MUXF5 to the F5 output of the slice.
and MUXF5 to the XMUX output of the slice.
Propagation delay from the F/G inputs of the slice, through the LUTs
www.xilinx.com
D
D
MUXF5
MUXFX
Figure
Description
5-20. Some elements of the Virtex-4
CLB / Slice Timing Models
D
CE
CLK
SR
D
CE
CLK
SR
FF/LAT
FF/LAT
REV
REV
Q
Q
UG070_5_20_071504
FX
Y
YQ
F5
X
XQ
205
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