XC4VFX100-11FFG1152C Xilinx Inc, XC4VFX100-11FFG1152C Datasheet - Page 361
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XC4VFX100-11FFG1152C
Manufacturer Part Number
XC4VFX100-11FFG1152C
Description
IC FPGA VIRTEX-4FX 100K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX100-11FFG1152C
Number Of Logic Elements/cells
94896
Number Of Labs/clbs
10544
Total Ram Bits
6930432
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Company:
Part Number:
XC4VFX100-11FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Figure 7-27
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
At time T
synchronous reset in this case) becomes valid-High resetting ODDR Register 1, reflected at
the OQ output at time T
and resetting ODDR Register 2, reflected at the OQ output at time T
(no change at the OQ output in this case).
OCE
At time T
High at the OCE input of the ODDR registers, enabling them for incoming data. Since
the OCE signal is common to all ODDR registers, care must be taken to toggle this
signal between the rising edges and falling edges of C as well as meeting the register
setup-time relative to both clock edges.
At time T
valid-High at the D1 input of ODDR register 1 and is reflected on the OQ output at
time T
At time T
valid-High at the D2 input of ODDR register 2 and is reflected on the OQ output at
time T
OQ
SR
D1
D2
C
T
OCKQ
OSRCK
OCKQ
OCKQ
illustrates the OLOGIC ODDR register timing.
Figure 7-27: OLOGIC ODDR Register Timing Characteristics
OOCECK
ODCK
ODCK
1
before Clock Event 9 (rising edge of C), the SR signal (configured as
after Clock Event 1.
after Clock Event 2 (no change at the OQ output in this case).
T
T
OOCECK
before Clock Event 1 (rising edge of C), the data signal D1 becomes
before Clock Event 2 (falling edge of C), the data signal D2 becomes
ODCK
2
before Clock Event 1, the ODDR clock enable signal becomes valid-
RQ
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after Clock Event 9 (no change at the OQ output in this case)
3
T
ODCK
4
5
6
T
OSRCK
7
8
RQ
9
OLOGIC Resources
after Clock Event 10
10
T
ug070_7_27_080204
RQ
11
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