XC5VLX110T-3FF1738C Xilinx Inc, XC5VLX110T-3FF1738C Datasheet - Page 344
XC5VLX110T-3FF1738C
Manufacturer Part Number
XC5VLX110T-3FF1738C
Description
IC FPGA VIRTEX-5 110K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FF1738C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
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Quantity:
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Part Number:
XC5VLX110T-3FF1738C
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Chapter 7: SelectIO Logic Resources
OLOGIC Resources
344
X-Ref Target - Figure 7-21
Instantiating Multiple IDELAYCTRLs Without LOC Constraints
Instantiating multiple IDELAYCTRL instances without LOC properties is prohibited. If
this occurs, an error is issued by the implementation tools.
OLOGIC consists of two major blocks, one to configure the output data path and the other
to configure the 3-state control path. These two blocks have a common clock (CLK) but
different enable signals, OCE and TCE. Both have asynchronous and synchronous set and
reset (SR and REV signals) controlled by an independent SRVAL attribute as described in
the
RST_NOLOC
Table 7-1
REFCLK
and
Figure 7-21: Mixed Instantiation of IDELAYCTRL Elements
Table
.
.
.
.
.
.
rst_1
rst_2
rst_n
7-2.
www.xilinx.com
.
.
.
all IDELAYCTRL
Replicated for
Instantiated without
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL_noloc
IDELAYCTRL_noloc
IDELAYCTRL_noloc
Instantiated with
LOC Constraint
LOC Constraint
IDELAYCTRL_1
IDELAYCTRL_2
IDELAYCTRL_n
sites
.
.
.
.
.
.
RDY
RDY
RDY
RDY
RDY
RDY
Auto-generated
by mapper tool
rdy_1
rdy_2
rdy_n
.
.
.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RDY_NOLOC
ug190_7_16_041306
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