XC5VLX110T-3FF1738C Xilinx Inc, XC5VLX110T-3FF1738C Datasheet - Page 90
XC5VLX110T-3FF1738C
Manufacturer Part Number
XC5VLX110T-3FF1738C
Description
IC FPGA VIRTEX-5 110K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FF1738C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
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- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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Chapter 3: Phase-Locked Loops (PLLs)
X-Ref Target - Figure 3-1
90
From any IBUFG implementation
From any BUFG implementation
Phase Locked Loop (PLL)
Virtex-5 devices contain up to six CMT tiles. The PLLs main purpose is to serve as a
frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for
either external or internal clocks in conjunction with the DCMs of the CMT.
The PLL block diagram shown in
components.
X-Ref Target - Figure 3-2
Clock Pin
Figure 3-1: Block Diagram of the Virtex-5 FPGA CMT
Figure 3-2: Block Diagram of the Virtex-5 FPGA PLL
D
www.xilinx.com
PFD
Figure 3-2
DCM1
DCM2
PLL
M
CP
provides a general overview of the PLL
LF
clkout_pll<5:0>
VCO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
To any BUFG
implementation
To any BUFG
implementation
To any BUFG
implementation
UG190_c3_01_022709
O0
O1
O2
O3
O4
O5
ug190_3_02_030506
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