XC5VSX95T-1FFG1136I Xilinx Inc, XC5VSX95T-1FFG1136I Datasheet - Page 126
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XC5VSX95T-1FFG1136I
Manufacturer Part Number
XC5VSX95T-1FFG1136I
Description
IC FPGA VIRTEX-5 95K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-1FFG1136I
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 4: Block RAM
Table 4-6: Port Aspect Ratio for RAMB18 and RAMB18SDP
Table 4-7: Port Aspect Ratio for RAMB36
126
72 (RAMB36SDP)
Port Data Width
36 (RAMB18SDP)
Port Data Width
1 (Cascade)
18
36
18
1
2
4
9
1
2
4
9
Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0>
Data-Out Buses - DO[A|B]<#:0> and DOP[A|B]<#:0>
Port Address Width
Port Address Width
For cascadable block RAM using the RAMB36, the data width is one bit, and the address
bus is 16 bits <15:0>. The address bit 15 is only used in cascadable block RAM. For non-
cascading block RAM, connect High.
Data and address pin mapping is further described in the
RAMB36 Primitive Design
Data-in buses provide the new data value to be written into RAM. The regular data-in bus
(DI), plus the parity data-in bus (DIP) when available, have a total width equal to the port
width. For example the 36-bit port data width is represented by DI<31:0> and DIP<3:0>, as
shown in
Data-out buses reflect the contents of memory cells referenced by the address bus at the
last active clock edge during a read operation. During a write operation (WRITE_FIRST or
READ_FIRST configuration), the data-out buses reflect either the data being written or the
stored value before write. During a write operation in NO_CHANGE mode, data-out
buses are not changed. The regular data-out bus (DO) plus the parity data-out bus (DOP)
(when available) have a total width equal to the port width, as shown in
Table
4-7.
15
14
13
12
11
10
16
9
14
13
12
11
10
9
Table 4-6
and
Depth
32,768
16,384
65536
8,192
4,096
2,048
1,024
Depth
16,384
512
8,192
4,096
2,048
1,024
512
Table
www.xilinx.com
Considerationssection.
4-7.
ADDR Bus
ADDR Bus
<14:0>
<14:1>
<14:2>
<14:3>
<14:4>
<14:5>
<14:6>
<15:0>
<13:0>
<13:1>
<13:2>
<13:3>
<13:4>
<13:5>
DI Bus / DO Bus
DI Bus / DO Bus
<15:0>
<31:0>
<63:0>
<1:0>
<3:0>
<7:0>
<15:0>
<31:0>
<0>
<0>
<1:0>
<3:0>
<7:0>
<0>
Additional RAMB18 and
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIP Bus / DOP Bus
DIP Bus / DOP Bus
Table 4-6
<1:0>
<3:0>
<7:0>
<1:0>
<3:0>
<0>
NA
NA
NA
NA
<0>
NA
NA
NA
and
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