XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 17
XC5VLX220T-1FFG1738C
Manufacturer Part Number
XC5VLX220T-1FFG1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-1FFG1738C
Total Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Macrocells
220000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
680
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Chapter 7: SelectIO Logic Resources
Rules for Combining I/O Standards in the Same Bank
Simultaneous Switching Output Limits
Introduction
ILOGIC Resources
Input/Output Delay Element (IODELAY)
SSTL2 Class II (2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Differential SSTL2 Class II (2.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . 284
SSTL18 Class I (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Differential SSTL Class I (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
SSTL18 Class II (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Differential SSTL Class II (1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination . . . . . . . . . . . . . . . . . . . . . . . . . 293
Differential Termination: DIFF_TERM Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
LVDS and Extended LVDS (Low Voltage Differential Signaling) . . . . . . . . . . . . . . . 294
HyperTransport Protocol (HT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Reduced Swing Differential Signaling (RSDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
BLVDS (Bus LVDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic) . . . . . . . . . . . 297
3.3V I/O Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Sparse-Chevron Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Nominal PCB Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Nominal SSO Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Actual SSO Limits versus Nominal SSO Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Electrical Basis of SSO Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Parasitic Factors Derating Method (PFDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Weighted Average Calculation of SSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Full Device SSO Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Other SSO Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Combinatorial Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Input DDR Overview (IDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Input DDR Primitive (IDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
IDDR VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
ILOGIC Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Transmitter Termination
Receiver Termination
LVPECL Transceiver Termination
I/O Standard Design Rules
Mixing Techniques
PCB Construction
Signal Return Current Management
Load Traces
Power Distribution System Design
LVDCI and HSLVDCI Drivers
Bank 0
OPPOSITE_EDGE Mode
SAME_EDGE Mode
SAME_EDGE_PIPELINED Mode
ILOGIC Timing Characteristics
ILOGIC Timing Characteristics, DDR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
www.xilinx.com
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
. . . . . . . . . . . . . . . . . . . . . . 298
17
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