XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 382
XC5VLX220T-1FFG1738C
Manufacturer Part Number
XC5VLX220T-1FFG1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-1FFG1738C
Total Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Macrocells
220000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
680
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Chapter 8: Advanced SelectIO Logic Resources
382
OSERDES VHDL and Verilog Instantiation Templates
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two OSERDES causes the SR input to come out of reset on two different
CLK cycles. Without internal retiming, OSERDES1 finishes reset one CLK cycle before
OSERDES0 and both OSERDES are asynchronous.
Clock Event 3
The release of the reset signal at the SR input is retimed internally to CLKDIV. This
synchronizes OSERDES0 and OSERDES1.
Clock Event 4
The release of the reset signal at the SR input is retimed internally to CLK.
The Libraries Guide includes instantiation templates of the OSERDES module in VHDL
and Verilog.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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