XC5VLX220-2FFG1760C Xilinx Inc, XC5VLX220-2FFG1760C Datasheet - Page 164
XC5VLX220-2FFG1760C
Manufacturer Part Number
XC5VLX220-2FFG1760C
Description
IC FPGA VIRTEX-5 220K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220-2FFG1760C
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7077888
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
800
Ram Bits
7077888
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220-2FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220-2FFG1760C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Chapter 4: Block RAM
Table 4-23: Block RAM (RAMB36SDP) Attributes
Table 4-24: FIFO (FIFO36_72) Attributes
164
EN_ECC_WRITE
EN_ECC_READ
DO_REG
EN_SYN
ALMOST_EMPTY_OFFSET
ALMOST_FULL_OFFSET
FIRST_WORD_FALL_THROUGH
EN_ECC_WRITE
EN_ECC_READ
DO_REG
Attribute Name
Attribute Name
Block RAM and FIFO ECC Attributes
1-bit Binary
In addition to the built-in registers in the decode and correct logic, the RAMB36SDP
primitive allows the use of optional pipeline registers controlled by the DO_REG attribute
to produce higher performance with one additional latency.
the block RAM and FIFO ECC attributes.
Boolean
Boolean
Type
Boolean TRUE, FALSE
Boolean TRUE, FALSE
Boolean TRUE, FALSE
Boolean TRUE, FALSE
Binary
Type
1-bit
9-bit
9-bit
Hex
Hex
TRUE, FALSE
TRUE, FALSE
Values
See
See
0, 1
Values
Table 4-19
Table 4-19
0, 1
www.xilinx.com
See
See
Default
FALSE
FALSE
Default
FALSE
FALSE
FALSE
FALSE
Table 4-19
Table 4-19
0
1
enable ECC functionality in a
FIFO36_72.
Enables register mode or latch mode. See
Table 4-17
synchronous FIFOs.
When set to TRUE, ties WRCLK and
RDCLK together.
When set to TRUE, FWFT must be
FALSE.
When set to FALSE, DO_REG must be 1.
Setting determines the difference
between EMPTY and ALMOST_EMPTY
conditions. Must be set using
hexadecimal notation.
Setting determines the difference
between FULL and ALMOST_FULL
conditions. Must be set using
hexadecimal notation.
When set to TRUE, the first word written
into the empty FIFO36_72 appears at the
FIFO36_72 output without RDEN
asserted.
Both attributes must be set to TRUE to
Set to TRUE to enable ECC encoder.
Set to TRUE to enable ECC decoder.
Enables register mode or latch mode.
Table 4-23
for details on multirate and
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Notes
Notes
and
Table 4-24
list
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